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* [AVR] Re-enable expansion of ADDE/ADDC/SUBE/SUBC in ISelDylan McKay2018-07-291-0/+7
| | | | | | | | | This was disabled in r333748, which broke four tests. In the future, these need to be updated to UADDO/ADDCARRY or USUBO/SUBCARRY. llvm-svn: 338212
* [AVR] Document some public functionsDylan McKay2018-07-151-0/+2
| | | | llvm-svn: 337122
* [AVR] Set trackLivenessAfterRegAllocDylan McKay2018-06-111-0/+5
| | | | | | | | | | | | | | | | | This sets trackLivenessAfterRegAlloc on AVRRegisterInfo. Most existing targets set this flag. Without it, specific IR inputs cause LLVM to fail with: Assertion failed: (getParent()->getProperties().hasProperty( MachineFunctionProperties::Property::TracksLiveness) && "Liveness information is accurate"), function livein_begin file MachineBasicBlock.cpp, line 1354. With this commit, this no longer happens. Patch by Peter Nimmervoll. llvm-svn: 334409
* [AVR] Fix build after r334078Alex Bradbury2018-06-072-4/+10
| | | | | | | r334078 added MCSubtargetInfo to fixupNeedsRelaxation and applyFixup. This patch makes the necessary adjustment for the AVR target. llvm-svn: 334202
* MC: Separate creating a generic object writer from creating a target object ↵Peter Collingbourne2018-05-214-12/+9
| | | | | | | | | | | | | writer. NFCI. With this we gain a little flexibility in how the generic object writer is created. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47045 llvm-svn: 332868
* MC: Change MCAsmBackend::writeNopData() to take a raw_ostream instead of an ↵Peter Collingbourne2018-05-212-5/+4
| | | | | | | | | | | | | MCObjectWriter. NFCI. To make this work I needed to add an endianness field to MCAsmBackend so that writeNopData() implementations know which endianness to use. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47035 llvm-svn: 332857
* MC: Change the streamer ctors to take an object writer instead of a stream. ↵Peter Collingbourne2018-05-183-10/+15
| | | | | | | | | | | | | | NFCI. The idea is that a client that wants split dwarf would create a specific kind of object writer that creates two files, and use it to create the streamer. Part of PR37466. Differential Revision: https://reviews.llvm.org/D47050 llvm-svn: 332749
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-142-3/+3
| | | | | | | | | | | | | | | | The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
* [DebugInfo] Examine all uses of isDebugValue() for debug instructions.Shiva Chen2018-05-091-2/+2
| | | | | | | | | | | | | | | | | | Because we create a new kind of debug instruction, DBG_LABEL, we need to check all passes which use isDebugValue() to check MachineInstr is debug instruction or not. When expelling debug instructions, we should expel both DBG_VALUE and DBG_LABEL. So, I create a new function, isDebugInstr(), in MachineInstr to check whether the MachineInstr is debug instruction or not. This patch has no new test case. I have run regression test and there is no difference in regression test. Differential Revision: https://reviews.llvm.org/D45342 Patch by Hsiangkai Wang. llvm-svn: 331844
* Remove duplicate tablegen lines from AVR target.Nico Weber2018-04-041-6/+2
| | | | | | | | | | They were added in r285274, in what looks like a merge mishap. AVRGenMCCodeEmitter.inc is the only non-dupe tablegen invocation added in that revision. Also sort the tablegen lines to make this easier to spot in the future. llvm-svn: 329178
* [AVR] Lower i128 divisions to runtime library callsDylan McKay2018-03-191-0/+3
| | | | | | | | | | | This patch adds i128 division support by instruction LLVM to lower 128-bit divisions to the __udivmodti4 and __divmodti4 rtlib functions. This also adds test for 64-bit division and 128-bit division. Patch by Peter Nimmervoll. llvm-svn: 327814
* [AVR] Remove the earlyclobber flag from LDDWRdYQDylan McKay2018-03-061-2/+16
| | | | | | | | | | | | | | | | | Before I started maintaining the AVR backend, this instruction never originally used to have an earlyclobber flag. Some time afterwards (years ago), I must've added it back in, not realising that it was left out for a reason. This pseudo instrction exists solely to work around a long standing bug in the register allocator. Before this commit, the LDDWRdYQ pseudo was not actually working around any bug. With the earlyclobber flag removed again, the LDDWRdYQ pseudo now correctly works around PR13375 again. llvm-svn: 326774
* [AVR] Set the program address space in the data layoutDylan McKay2018-02-191-1/+1
| | | | | | | | | | | | This adds the program memory address space setting to the AVR data layout. This setting was very recently added under r325479. At the moment, there are no uses of this setting. In the future, things such as switch lookup tables should reside there. llvm-svn: 325481
* [AVR] Fix a lowering bug in AVRISelLowering.cppDylan McKay2018-02-191-4/+6
| | | | | | | | | | | | | | The parseFunctionArgs() method was directly reading the arguments from a Function object, but is should have used the arguments supplied by the SelectionDAGBuilder. This was causing the lowering code to only lower one argument, not two in some cases. Thanks to @brainlag on GitHub for coming up with the working fix! Patch-by: @brainlag on GitHub llvm-svn: 325474
* [SelectionDAGISel] Add a debug print before call to Select. Adjust where ↵Craig Topper2018-01-261-3/+0
| | | | | | | | | | | | blank lines are printed during isel process to make things more sensibly grouped. Previously some targets printed their own message at the start of Select to indicate what they were selecting. For the targets that didn't, it means there was no print of the root node before any custom handling in the target executed. So if the target did something custom and never called SelectNodeCommon, no print would be made. For the targets that did print a message in Select, if they didn't custom handle a node SelectNodeCommon would reprint the root node before walking the isel table. It seems better to just print the message before the call to Select so all targets behave the same. And then remove the root node printing from SelectNodeCommon and just leave a message that says we're starting the table search. There were also some oddities in blank line behavior. Usually due to a \n after a call to SelectionDAGNode::dump which already inserted a new line. llvm-svn: 323551
* Fix build of WebAssembly and AVR backends after r321692Alex Bradbury2018-01-032-5/+6
| | | | | | | As experimental backends, I didn't have them configured to build in my local build config. llvm-svn: 321696
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-153-5/+5
| | | | | | The Function can never be nullptr so we can return a reference. llvm-svn: 320884
* [AVR] Implement some missing code pathsDylan McKay2017-12-112-4/+19
| | | | | | This has been broken since r320009. llvm-svn: 320348
* [AVR] Fix incorrectly-calculated AVRMCExpr evaluationsDylan McKay2017-12-111-12/+9
| | | | | | This has been broken since r320009. llvm-svn: 320347
* Revert and accidentally committed revert commitDylan McKay2017-12-0911-22/+275
| | | | | | This reverts commit r320245. llvm-svn: 320247
* Revert "[AVR] Override ParseDirective"Dylan McKay2017-12-0911-275/+22
| | | | | | This reverts commit 57c16f9267969ebb09d6448607999b4a9f40c418. llvm-svn: 320245
* Relax unaligned access assertion when type is byte alignedDylan McKay2017-12-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This relaxes an assertion inside SelectionDAGBuilder which is overly restrictive on targets which have no concept of alignment (such as AVR). In these architectures, all types are aligned to 8-bits. After this, LLVM will only assert that accesses are aligned on targets which actually require alignment. This patch follows from a discussion on llvm-dev a few months ago http://llvm.1065342.n5.nabble.com/llvm-dev-Unaligned-atomic-load-store-td112815.html Reviewers: bogner, nemanjai, joerg, efriedma Reviewed By: efriedma Subscribers: efriedma, cactus, llvm-commits Differential Revision: https://reviews.llvm.org/D39946 llvm-svn: 320243
* [AVR] Override ParseDirectiveLeslie Zhai2017-12-0711-22/+275
| | | | | | | | | | Reviewers: dylanmckay, kparzysz Reviewed By: dylanmckay Differential Revision: https://reviews.llvm.org/D38029 llvm-svn: 320009
* Add backend name to AVR Target to enable runtime info to be fed back into ↵Leslie Zhai2017-11-231-1/+1
| | | | | | TableGen llvm-svn: 318895
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-176-7/+7
| | | | | | | | All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-081-1/+1
| | | | | | | | This header includes CodeGen headers, and is not, itself, included by any Target headers, so move it into CodeGen to match the layering of its implementation. llvm-svn: 317647
* Move TargetFrameLowering.h to CodeGen where it's implementedDavid Blaikie2017-11-032-2/+2
| | | | | | | | | | | This header already includes a CodeGen header and is implemented in lib/CodeGen, so move the header there to match. This fixes a link error with modular codegeneration builds - where a header and its implementation are circularly dependent and so need to be in the same library, not split between two like this. llvm-svn: 317379
* [AVR] Update to current LLVM APIDylan McKay2017-10-185-9/+19
| | | | | | | r315410 broke a number of things in the AVR backend, which are now fixed. llvm-svn: 316076
* Revert "TargetMachine: Merge TargetMachine and LLVMTargetMachine"Matthias Braun2017-10-122-4/+6
| | | | | | | | | | Reverting to investigate layering effects of MCJIT not linking libCodeGen but using TargetMachine::getNameWithPrefix() breaking the lldb bots. This reverts commit r315633. llvm-svn: 315637
* TargetMachine: Merge TargetMachine and LLVMTargetMachineMatthias Braun2017-10-122-6/+4
| | | | | | | | | | | | | | | Merge LLVMTargetMachine into TargetMachine. - There is no in-tree target anymore that just implements TargetMachine but not LLVMTargetMachine. - It should still be possible to stub out all the various functions in case a target does not want to use lib/CodeGen - This simplifies the code and avoids methods ending up in the wrong interface. Differential Revision: https://reviews.llvm.org/D38489 llvm-svn: 315633
* [Asm] Add debug tracing in table-generated assembly matcherOliver Stannard2017-10-111-1/+1
| | | | | | | | | | | | | This adds debug tracing to the table-generated assembly instruction matcher, enabled by the -debug-only=asm-matcher option. The changes in the target AsmParsers are to add an MCInstrInfo reference under a consistent name, so that we can use it from table-generated code. This was already being used this way for targets that use deprecation warnings, but 5 targets did not have it, and Hexagon had it under a different name to the other backends. llvm-svn: 315445
* [AVR] Implement LPMWRdZ pseudo-instruction's expansion.Dylan McKay2017-10-041-1/+44
| | | | | | | | | FIXME: implementation is mostly copy-pasted from LDWRdPtr, so we should refactor a bit and unify the two Patch by Gerdo Erdi. llvm-svn: 314898
* [AVR] Factor out mayLoad in tablegen patternsDylan McKay2017-10-041-2/+2
| | | | | | Patch by Gergo Erdi. llvm-svn: 314897
* [AVR] Elaborate LDWRdPtr into `ld r, X++; ld r+1, X`Dylan McKay2017-10-042-7/+7
| | | | | | Patch by Gergo Erdi. llvm-svn: 314896
* [AVR] Insert JMP for long branchesDylan McKay2017-10-042-2/+22
| | | | | | | | | | | Previously, on long branches (relative jumps of >4 kB), an assertion failure was hit, as AVRInstrInfo::insertIndirectBranch was not implemented. Despite its name, it is called by the branch relaxator for *all* unconditional jumps. Patch by Thomas Backman. llvm-svn: 314891
* [AVR] Fix displacement overflow for LDDW/STDWDylan McKay2017-10-042-5/+13
| | | | | | | | | | | | | | | | | | | In some cases, the code generator attempts to generate instructions such as: lddw r24, Y+63 which expands to: ldd r24, Y+63 ldd r25, Y+64 # Oops! This is actually ld r25, Y in the binary This commit limits the first offset to 62, and thus the second to 63. It also updates some asserts in AVRExpandPseudoInsts.cpp, including for INW and OUTW, which appear to be unused. Patch by Thomas Backman. llvm-svn: 314890
* [AVR] Prefer BasicBlock::getIterator over Function::begin()Dylan McKay2017-09-261-1/+1
| | | | | | Thanks to Eli Friedman for the suggestion. llvm-svn: 314182
* [AVR] When lowering shifts into loops, put newly generated MBBs in the sameDylan McKay2017-09-261-2/+4
| | | | | | | | | | | spot as the original MBB Discovered in avr-rust/rust#62 https://github.com/avr-rust/rust/issues/62 Patch by Gergo Erdi. llvm-svn: 314180
* [AVR] Use 1-byte alignment for all data typesDylan McKay2017-09-261-1/+1
| | | | | | | | | | | | | | This was an oversight in the original backend data layout. The AVR architecture does not have the concept of unaligned loads - all loads/stores from all addresses are aligned to one byte. Discovered in avr-rust issue #64 https://github.com/avr-rust/rust/issues/64 Patch By Gergo Erdi. llvm-svn: 314179
* [AVR] Implement getCmpLibcallReturnType().Dylan McKay2017-09-241-0/+5
| | | | | | | | | This fixes the avr-rust issue (#75) with floating-point comparisons generating broken code. By default, LLVM assumes these comparisons return 32-bit values, but ours are 8-bit. Patch By Thomas Backman. llvm-svn: 314070
* [AVR] Remove the 'IsN64' argument to 'MCELFObjectWriter'Dylan McKay2017-09-221-1/+1
| | | | | | This has since been removed. llvm-svn: 313965
* [AVR] Enable the '__do_copy_data' functionDylan McKay2017-09-112-0/+22
| | | | | | | | | | | | | Also enables '__do_clear_bss'. These functions are automaticalled called by the CRT if they are declared. We need these to be called otherwise RAM will start completely uninitialised, even though we need to copy RAM variables from progmem to RAM. llvm-svn: 312905
* [AVR] Use the correct register classes for 16-bit atomic operationsDylan McKay2017-08-241-22/+42
| | | | llvm-svn: 311620
* Add "Restored" flag to CalleeSavedInfoKrzysztof Parzyszek2017-08-102-2/+2
| | | | | | | | | | | The liveness-tracking code assumes that the registers that were saved in the function's prolog are live outside of the function. Specifically, that registers that were saved are also live-on-exit from the function. This isn't always the case as illustrated by the LR register on ARM. Differential Revision: https://reviews.llvm.org/D36160 llvm-svn: 310619
* [AVR] Compute code model if one is not providedMeador Inge2017-08-061-6/+10
| | | | | | | | | | | | | | The patch from r310028 fixed things to work with the new `LLVMTargetMachine` constructor that came in on r309911. However, the fix was partial since an object of type `CodeModel::Model` must be passed to `LLVMTargetMachine` (not one of `Optional<CodeModel::Model>`). This patch fixes the problem in the same fashion that r309911 did for other machines: by checking if the passed optional code model has a value and using `CodeModel::Small` if not. llvm-svn: 310200
* [AVR] Update target machine to use new constructor parametersDylan McKay2017-08-042-5/+10
| | | | | | The required parameters were changed in r309911. llvm-svn: 310028
* [AVR] Remove the instrumentation passDylan McKay2017-07-234-226/+0
| | | | | | | | I have a much better way of running integration tests now. https://github.com/dylanmckay/avr-test-suite llvm-svn: 308857
* [SystemZ, LoopStrengthReduce]Jonas Paulsson2017-07-212-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes LSR generate better code for SystemZ in the cases of memory intrinsics, Load->Store pairs or comparison of immediate with memory. In order to achieve this, the following common code changes were made: * New TTI hook: LSRWithInstrQueries(), which defaults to false. Controls if LSR should do instruction-based addressing evaluations by calling isLegalAddressingMode() with the Instruction pointers. * In LoopStrengthReduce: handle address operands of memset, memmove and memcpy as address uses, and call isFoldableMemAccessOffset() for any LSRUse::Address, not just loads or stores. SystemZ changes: * isLSRCostLess() implemented with Insns first, and without ImmCost. * New function supportedAddressingMode() that is a helper for TTI methods looking at Instructions passed via pointers. Review: Ulrich Weigand, Quentin Colombet https://reviews.llvm.org/D35262 https://reviews.llvm.org/D35049 llvm-svn: 308729
* [AVR] Fix broken indentationDylan McKay2017-07-131-1/+1
| | | | llvm-svn: 307891
* [AVR] Add a 'LLVM_FALLTHROUGH' statement to the AsmParserDylan McKay2017-07-131-0/+1
| | | | | | Should fix warnings in the build. llvm-svn: 307890
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