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* Fix assert.Eric Christopher2012-01-111-2/+2
| | | | llvm-svn: 147966
* ARM Ld/St Optimizer fix.Andrew Trick2012-01-111-3/+4
| | | | | | | | Allow LDRD to be formed from pairs with different LDR encodings. This was the original intention of the pass. Somewhere along the way, the LDR opcodes were refined which broke the optimization. We really don't care what the original opcodes are as long as they both map to the same LDRD and the immediate still fits. Fixes rdar://10435045 ARMLoadStoreOptimization cannot handle mixed LDRi8/LDRi12 llvm-svn: 147922
* Consider unknown alignment caused by OptimizeThumb2Instructions().Jakob Stoklund Olesen2012-01-101-4/+25
| | | | | | | | | | | | | | | | | | | | This function runs after all constant islands have been placed, and may shrink some instructions to their 2-byte forms. This can actually cause some constant pool entries to move out of range because of growing alignment padding. Treat instructions that may be shrunk the same as inline asm - they erode the known alignment bits. Also reinstate an old assertion in verify(). It is correct now that basic block offsets include alignments. Add a single large test case that will hopefully exercise many parts of the constant island pass. <rdar://problem/10670199> llvm-svn: 147885
* ARM updating VST2 pseudo-lowering fixed vs. register update.Jim Grosbach2012-01-103-8/+8
| | | | | | rdar://10663487 llvm-svn: 147876
* Move default case for covered enum outside of switch.Richard Smith2012-01-101-1/+1
| | | | llvm-svn: 147870
* Fix a -Wreturn-type warning in g++.Richard Smith2012-01-101-0/+1
| | | | llvm-svn: 147867
* Remove unnecessary default cases in switches that cover all enum values.David Blaikie2012-01-103-4/+0
| | | | llvm-svn: 147855
* Accurately model hardware alignment rounding.Jakob Stoklund Olesen2012-01-101-21/+56
| | | | | | | | | | | | | | | | | | | On Thumb, the displacement computation hardware uses the address of the current instruction rouned down to a multiple of 4. Include this rounding in the UserOffset we compute for each instruction. When inline asm is present, the instruction alignment may not be known. Constrain the maximum displacement instead in that case. This makes it possible for CreateNewWater() and OffsetIsInRange() to agree about the valid displacements. When they disagree, infinite looping happens. As always, test cases for this stuff are insane. <rdar://problem/10660175> llvm-svn: 147825
* Catch runaway ARMConstantIslandPass even in -Asserts builds.Jakob Stoklund Olesen2012-01-091-2/+2
| | | | | | | | | The pass is prone to looping, and it is better to crash than loop forever, even in a -Asserts build. <rdar://problem/10660175> llvm-svn: 147806
* Don't forget to transfer implicit uses of return instruction.Evan Cheng2012-01-081-2/+5
| | | | llvm-svn: 147752
* Match SelectionDAG logic for enabling movt.Jakob Stoklund Olesen2012-01-072-2/+7
| | | | | | Darwin doesn't do static, and ELF targets only support static. llvm-svn: 147740
* Remove VectorExtras. This unused helper was written for a type of API that ↵Benjamin Kramer2012-01-071-1/+0
| | | | | | is discouraged now. llvm-svn: 147738
* Use getRegForValue() to materialize the address of ARM globals.Jakob Stoklund Olesen2012-01-071-10/+0
| | | | | | | | | This enables basic local CSE, giving us 20% smaller code for consumer-typeset in -O0 builds. <rdar://problem/10658692> llvm-svn: 147720
* Copy implicit defs (e.g. r0) when changing tBX_RET to tPOP_RET. This bug isEvan Cheng2012-01-071-0/+1
| | | | | | | exposed with an upcoming change will would delete the copy to return register because there is no use! It's amazing anything works. llvm-svn: 147715
* Use movw+movt in ARMFastISel::ARMMaterializeGV.Jakob Stoklund Olesen2012-01-071-29/+50
| | | | | | | | | | | | | This eliminates a lot of constant pool entries for -O0 builds of code with many global variable accesses. This speeds up -O0 codegen of consumer-typeset by 2x because the constant island pass no longer has to look at thousands of constant pool entries. <rdar://problem/10629774> llvm-svn: 147712
* Enable aligned NEON spilling by default.Jakob Stoklund Olesen2012-01-061-1/+1
| | | | | | Experiments show this to be a small speedup for modern ARM cores. llvm-svn: 147689
* Abort AdjustBBOffsetsAfter early when possible.Jakob Stoklund Olesen2012-01-061-2/+10
| | | | llvm-svn: 147685
* Reapply r146997, "Heed spill slot alignment on ARM."Jakob Stoklund Olesen2012-01-052-3/+4
| | | | | | | | | | | | Now that canRealignStack() understands frozen reserved registers, it is safe to use it for aligned spill instructions. It will only return true if the registers reserved at the beginning of register allocation allow for dynamic stack realignment. <rdar://problem/10625436> llvm-svn: 147579
* Avoid reserving an ARM base pointer during register allocation.Jakob Stoklund Olesen2012-01-051-2/+17
| | | | | | | | | | | | | | | | | Once register allocation has started the reserved registers are frozen. Fix the ARM canRealignStack() hook to respect the frozen register state. Now the hook returns false if register allocation was started with frame pointer elimination enabled. It also returns false if register allocation started without a reserved base pointer, and stack realignment would require a base pointer. This bug was breaking oggenc on armv6. No test case, an upcoming patch will use this functionality to realign the stack for spill slots when possible. llvm-svn: 147578
* Fix more places which should be checking for iOS, not darwin.Evan Cheng2012-01-043-18/+18
| | | | llvm-svn: 147513
* Revert r146997, "Heed spill slot alignment on ARM."Jakob Stoklund Olesen2012-01-032-4/+3
| | | | | | | | | This patch caused a miscompilation of oggenc because a frame pointer was suddenly needed halfway through register allocation. <rdar://problem/10625436> llvm-svn: 147487
* Fix malformed assert.Matt Beaumont-Gay2012-01-031-1/+1
| | | | | | | | If anybody has strong feelings about 'default: assert(0 && "blah")' vs 'default: llvm_unreachable("blah")', feel free to regularize the instances of each in this file. llvm-svn: 147459
* Fix Comments.Jakob Stoklund Olesen2011-12-241-3/+3
| | | | llvm-svn: 147238
* Experimental support for aligned NEON spills.Jakob Stoklund Olesen2011-12-233-13/+377
| | | | | | | | | | | | | ARM targets with NEON units have access to aligned vector loads and stores that are potentially faster than unaligned operations. Add support for spilling the callee-saved NEON registers to an aligned stack area using 16-byte aligned NEON loads and store. This feature is off by default, controlled by an -align-neon-spills command line option. llvm-svn: 147211
* Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138>Bob Wilson2011-12-224-7/+23
| | | | | | | | | | | My change r146949 added register clobbers to the eh_sjlj_dispatchsetup pseudo instruction, but on Thumb1 some of those registers cannot be used. This caused massive failures on the testsuite when compiling for Thumb1. While fixing that, I noticed that the eh_sjlj_setjmp instruction has a "nofp" variant, and I realized that dispatchsetup needs the same thing, so I have added that as well. llvm-svn: 147204
* ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).Jim Grosbach2011-12-224-16/+70
| | | | | | rdar://10558523 llvm-svn: 147189
* Add missing usesCustomInserter flag on Int_eh_sjlj_setjmp_nofp.Bob Wilson2011-12-221-1/+1
| | | | | | Noticed by inspection; I don't have a testcase for this. llvm-svn: 147188
* Tidy up. Use predicate function a bit more liberally.Jim Grosbach2011-12-221-97/+52
| | | | llvm-svn: 147184
* Fix incorrect relocation generation. Patch by Kristof Beyls.Rafael Espindola2011-12-221-8/+1
| | | | | | Fixes PR11214. llvm-svn: 147180
* ARM VFP add encoding of the bitcount to fixed-point<-->floating point. insns.Jim Grosbach2011-12-221-0/+3
| | | | | | | | | | The value from the operands isn't right yet, but we weren't encoding it at all previously. The parser needs to twiddle the values when building the instruction. Partial for: rdar://10558523 llvm-svn: 147170
* Remove some bogus comments.Jim Grosbach2011-12-221-36/+18
| | | | llvm-svn: 147169
* ARM pre-UAL aliases. fcmp[sd].Jim Grosbach2011-12-222-1/+3
| | | | llvm-svn: 147158
* ARM assembler should accept shift-by-zero for any shifted-immediate operand.Jim Grosbach2011-12-221-0/+33
| | | | | | | | Just treat it as-if the shift wasn't there at all. 'as' compatibility. rdar://10604767 llvm-svn: 147153
* ARM assembly parser canonicallize on 'lsl' for shift-by-zero form.Jim Grosbach2011-12-221-0/+4
| | | | llvm-svn: 147152
* Tidy up. Trailing whitespace.Jim Grosbach2011-12-221-2/+2
| | | | llvm-svn: 147151
* Nuke invalid comment from copy/paste.Jim Grosbach2011-12-221-1/+0
| | | | llvm-svn: 147150
* Make the virtual methods in ARMELFObjectWriter public.Rafael Espindola2011-12-221-7/+6
| | | | llvm-svn: 147132
* Hopefully fix the cmake build.Rafael Espindola2011-12-221-0/+1
| | | | llvm-svn: 147121
* Fix name in comments.Rafael Espindola2011-12-221-1/+1
| | | | llvm-svn: 147119
* Unbreak cmake build after r147115.Richard Smith2011-12-221-0/+1
| | | | llvm-svn: 147117
* Move the ARM specific parts of the ELF writer to Target/ARM.Rafael Espindola2011-12-223-2/+291
| | | | llvm-svn: 147115
* ARM NEON mnemonic aliase for vrecpeq.Jim Grosbach2011-12-211-0/+3
| | | | llvm-svn: 147109
* ARM VFP optional data type on VMOV GPR<-->SPR.Jim Grosbach2011-12-211-3/+11
| | | | llvm-svn: 147104
* ARM NEON optional data type on VSWP instructions.Jim Grosbach2011-12-211-0/+6
| | | | llvm-svn: 147103
* ARM NEON mnemonic aliases for vzipq and vswpq.Jim Grosbach2011-12-211-0/+3
| | | | llvm-svn: 147102
* ARM asm parser should be more lenient w/ .thumb_func directive.Jim Grosbach2011-12-211-8/+17
| | | | | | | | | | Rather than require the symbol to be explicitly an argument of the directive, allow it to look ahead and grab the symbol from the next non-whitespace line. rdar://10611140 llvm-svn: 147100
* Thumb2 assembly parsing of 'mov rd, rn, rrx'.Jim Grosbach2011-12-211-1/+3
| | | | | | | | Maps to the RRX instruction. Missed this case earlier. rdar://10615373 llvm-svn: 147096
* Thumb2 assembly parsing of 'mov(register shifted register)' aliases.Jim Grosbach2011-12-212-0/+41
| | | | | | | | These map to the ASR, LSR, LSL, ROR instruction definitions. rdar://10615373 llvm-svn: 147094
* Move common code into an MRI function.Jakob Stoklund Olesen2011-12-211-10/+1
| | | | llvm-svn: 147071
* ARM NEON assmebly parsing for VLD2 to all lanes instructions.Jim Grosbach2011-12-214-30/+70
| | | | llvm-svn: 147069
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