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* Let target asm backends see assembler flags as they go by. Use that to handleJim Grosbach2010-12-081-5/+28
| | | | | | thumb vs. arm mode differences in WriteNopData(). llvm-svn: 121219
* Simplify the byte reordering logic slightly.Owen Anderson2010-12-081-4/+2
| | | | llvm-svn: 121216
* VLDR fixups need special handling under Thumb. While the encoding is the same,Owen Anderson2010-12-083-2/+23
| | | | | | the order of the bytes in the data stream is flipped around. llvm-svn: 121215
* Fix a warning about a variable which is only used in an assertion.Matt Beaumont-Gay2010-12-071-2/+2
| | | | llvm-svn: 121206
* Cleanup in the Darwin end. No functionality change.Bill Wendling2010-12-071-5/+7
| | | | llvm-svn: 121198
* Fix a bad prologue / epilogue codegen bug where the compiler would emit illegalEvan Cheng2010-12-072-68/+92
| | | | | | | | | | | vpush instructions to save / restore VFP / NEON registers like this: vpush {d8,d10,d11} vpop {d8,d10,d11} vpush and vpop do not allow gaps in the register list. rdar://8728956 llvm-svn: 121197
* A bit of cleanup: early exit ApplyFixup and cache the Fixup offset. NoBill Wendling2010-12-071-13/+14
| | | | | | functionality change. llvm-svn: 121195
* Binary encoding for ARM tLDRspi and tSTRspi.Jim Grosbach2010-12-073-8/+42
| | | | llvm-svn: 121186
* Fix Thumb2 encoding of the S bit.Owen Anderson2010-12-072-23/+4
| | | | llvm-svn: 121182
* Refactor the ARM CMPz* patterns to just use the normal CMP instructions whenJim Grosbach2010-12-076-41/+25
| | | | | | | possible. They were duplicates for everything exception the source pattern before. llvm-svn: 121179
* Code clean up; no functionality change.Evan Cheng2010-12-071-16/+14
| | | | llvm-svn: 121176
* Code clean up; no functionality change.Evan Cheng2010-12-071-11/+8
| | | | llvm-svn: 121172
* Encode the literal field for tCMPzi instruction.Jim Grosbach2010-12-071-1/+2
| | | | llvm-svn: 121153
* Add parens to pacify gcc.Benjamin Kramer2010-12-071-1/+1
| | | | llvm-svn: 121142
* PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() andJay Foad2010-12-071-1/+1
| | | | | | | | zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method trunc(), to be const and to return a new value instead of modifying the object in place. llvm-svn: 121120
* Second attempt at converting Thumb2's LDRpci, including updating the ↵Owen Anderson2010-12-078-72/+101
| | | | | | gazillion places that need to know about it. llvm-svn: 121082
* Add fixup for Thumb1 BL/BLX instructions.Jim Grosbach2010-12-065-17/+78
| | | | llvm-svn: 121072
* Remove the instruction fragment to data fragment lowering since it was causingRafael Espindola2010-12-061-9/+9
| | | | | | freed data to be read. I will open a bug to track it being reenabled. llvm-svn: 121028
* Revert r121021, which broke the buildbots.Owen Anderson2010-12-062-34/+20
| | | | llvm-svn: 121026
* Trailing whitespace.Jim Grosbach2010-12-061-1/+1
| | | | llvm-svn: 121024
* Improve handling of Thumb2 PC-relative loads by converting LDRpci (and ↵Owen Anderson2010-12-062-20/+34
| | | | | | friends) to Pseudos. llvm-svn: 121021
* Encode the register operand of ARM CondCode operands correctly. ARM::CPSR ifJim Grosbach2010-12-061-2/+2
| | | | | | the instruction is predicated, reg0 otherwise. llvm-svn: 121020
* The ARM AsmMatcher needs to know that the CCOut operand is a register value,Jim Grosbach2010-12-062-1/+27
| | | | | | not an immediate. It stores either ARM::CPSR or reg0. llvm-svn: 121018
* Eliminate unneeded #include's.Evan Cheng2010-12-051-2/+0
| | | | llvm-svn: 120971
* ARM/CMakeLists.txt: Add missing MLxExpansionPass.cpp since r120960.NAKAMURA Takumi2010-12-051-0/+1
| | | | llvm-svn: 120966
* Code clean up.Evan Cheng2010-12-051-6/+6
| | | | llvm-svn: 120965
* Remove an unused variable.Evan Cheng2010-12-051-2/+1
| | | | llvm-svn: 120964
* Making use of VFP / NEON floating point multiply-accumulate / subtraction isEvan Cheng2010-12-0519-191/+771
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | difficult on current ARM implementations for a few reasons. 1. Even though a single vmla has latency that is one cycle shorter than a pair of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause additional pipeline stall. So it's frequently better to single codegen vmul + vadd. 2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to stall for 4 cycles. We need to schedule them apart. 3. A vmla followed vmla is a special case. Obvious issuing back to back RAW vmla + vmla is very bad. But this isn't ideal either: vmul vadd vmla Instead, we want to expand the second vmla: vmla vmul vadd Even with the 4 cycle vmul stall, the second sequence is still 2 cycles faster. Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough but it isn't the optimial solution. This patch attempts to make it possible to use vmla / vmls in cases where it is profitable. A. Add missing isel predicates which cause vmla to be codegen'ed. B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to compute a fmul and a fmla. C. Add additional isel checks for vmla, avoid cases where vmla is feeding into fp instructions (except for the #3 exceptional case). D. Add ARM hazard recognizer to model the vmla / vmls hazards. E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the vmla / vmls will trigger one of the special hazards. Work in progress, only A+B are enabled. llvm-svn: 120960
* The Thumb tADDrSPi instruction is not valid when the destination is SP.Bob Wilson2010-12-041-1/+8
| | | | | | Check for that and try narrowing it to tADDspi instead. Radar 8724703. llvm-svn: 120892
* Encode condition code for Thumb1 conditional branch instruction.Jim Grosbach2010-12-041-3/+6
| | | | llvm-svn: 120865
* Correctly size-reduce the t2CMPzrr instruction to tCMPzr when possible.Jim Grosbach2010-12-031-1/+13
| | | | | | | tCMPzhir has undefined behavior when both source registers are low registers. rdar://8728577 llvm-svn: 120858
* Use correct variable names to match the patterns.Bill Wendling2010-12-031-13/+14
| | | | llvm-svn: 120857
* Match pattern operand names to expected encoding field names. This corrects theJim Grosbach2010-12-031-2/+2
| | | | | | operand encoding ordering of the instruction. llvm-svn: 120852
* Remove incorrect BL target encoding (it's similar to, but not the same as theJim Grosbach2010-12-031-16/+14
| | | | | | ARM instruction). Add encoding of bits 13 and 11. llvm-svn: 120849
* Encode the 32-bit wide Thumb (and Thumb2) instructions with the high orderJim Grosbach2010-12-031-1/+9
| | | | | | halfword being emitted to the stream first. rdar://8728174 llvm-svn: 120848
* When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's theJim Grosbach2010-12-031-0/+4
| | | | | | 32-bit wide version by adding the .w suffix. llvm-svn: 120838
* Remove unused variable.Benjamin Kramer2010-12-031-1/+0
| | | | llvm-svn: 120836
* Reduce t2 ldr/str instructions to the correct t1 versions when there's anJim Grosbach2010-12-031-6/+6
| | | | | | immediate offset. llvm-svn: 120833
* fix ARM::fixup_arm_branch, cleanup, and share more code between ELF and DarwinJason W Kim2010-12-031-23/+10
| | | | llvm-svn: 120832
* No need to declare EncoderMethod property anymore; just assign to it.Jim Grosbach2010-12-031-3/+3
| | | | llvm-svn: 120831
* Add FIXMEs.Jim Grosbach2010-12-031-0/+2
| | | | llvm-svn: 120824
* Size reduction for tPUSH come from t2STMDB_UPD, not t2STMIA_UPD.Jim Grosbach2010-12-031-1/+2
| | | | llvm-svn: 120822
* Don't overwrite the opcode passed into the T1Special pattern.Bill Wendling2010-12-031-4/+5
| | | | llvm-svn: 120782
* Add Thumb encoding for some more instructions.Bill Wendling2010-12-031-19/+68
| | | | llvm-svn: 120780
* The tLDR instruction wasn't encoded properly:Bill Wendling2010-12-031-2/+6
| | | | | | | | | <MCInst 2251 <MCOperand Reg:70> <MCOperand Reg:66> <MCOperand Imm:0> <MCOperand Reg:0> <MCOperand Imm:14> <MCOperand Reg:0>> Notice that the "reg" here is 0, which is an invalid register. Put a check in the code for this to prevent crashing. llvm-svn: 120766
* Trailing whitespace.Jim Grosbach2010-12-021-32/+32
| | | | llvm-svn: 120748
* When expanding the MOVCCi32imm, make sure to use the ARM movt/movw opcodes,Jim Grosbach2010-12-021-4/+5
| | | | | | not thumb2. llvm-svn: 120711
* Fix copy/pasto in vmin.f32 encoding.Jim Grosbach2010-12-021-1/+1
| | | | llvm-svn: 120709
* Add support for binary encoding of ARM 'adr' instructions referencing constantJim Grosbach2010-12-025-38/+56
| | | | | | pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291. llvm-svn: 120635
* Fix and re-enable tail call optimization of expanded libcalls.Evan Cheng2010-12-011-1/+4
| | | | llvm-svn: 120622
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