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* Fix .fpu printing in ARM assembly, regarding bug ↵Renato Golin2011-02-281-4/+38
| | | | | | http://llvm.org/bugs/show_bug.cgi?id=8931 llvm-svn: 126689
* Add missing whitespace in the formatting.Kevin Enderby2011-02-281-1/+1
| | | | llvm-svn: 126687
* Fix the arm's disassembler for blx that was building an MCInst without theKevin Enderby2011-02-281-1/+13
| | | | | | needed two predicate operands before the imm operand. llvm-svn: 126662
* Fix a typo which cause dag combine crash. rdar://9059537.Evan Cheng2011-02-281-1/+1
| | | | llvm-svn: 126661
* Support for byval parameters on ARM. Will be enabled by a forthcomingStuart Hastings2011-02-283-9/+47
| | | | | | patch to the front-end. Radar 7662569. llvm-svn: 126655
* Add patterns to use post-increment addressing for Neon VST1-lane instructions.Bob Wilson2011-02-253-11/+39
| | | | llvm-svn: 126477
* Fix typo.Evan Cheng2011-02-251-1/+1
| | | | llvm-svn: 126467
* Each prologue may have multiple vpush instructions to store callee-savedEvan Cheng2011-02-251-2/+14
| | | | | | | | | | | D registers since the vpush list may not have gaps. Make sure the stack adjustment instruction isn't moved between them. Ditto for vpop in epilogues. Sorry, can't reduce a small test case. rdar://9043312 llvm-svn: 126457
* Change VFPNeonA8 definition to make the code easier to read.Evan Cheng2011-02-232-8/+3
| | | | llvm-svn: 126298
* More fcopysign correctness and performance fix.Evan Cheng2011-02-231-33/+63
| | | | | | | | | | | | | The previous codegen for the slow path (when values are in VFP / NEON registers) was incorrect if the source is NaN. The new codegen uses NEON vbsl instruction to copy the sign bit. e.g. vmov.i32 d1, #0x80000000 vbsl d1, d2, d0 If NEON is not available, it uses integer instructions to copy the sign bit. rdar://9034702 llvm-svn: 126295
* VFP single precision arith instructions can go down to NEON pipeline, but on ↵Evan Cheng2011-02-226-109/+114
| | | | | | Cortex-A8 only. llvm-svn: 126238
* Guard against de-referencing MBB.end().Evan Cheng2011-02-221-1/+4
| | | | llvm-svn: 126192
* available_externally (hidden or not) GVs are always accessed via stubs. ↵Evan Cheng2011-02-221-1/+3
| | | | | | rdar://9027648. llvm-svn: 126191
* Only use blx for external function calls on thumb, these could be fixedEric Christopher2011-02-221-12/+26
| | | | | | | | | up by the dynamic linker, but it's better to use the correct instruction to begin with. Fixes rdar://9011034 llvm-svn: 126176
* Skipping over debugvalue instructions to determine whether the split spot is ↵Evan Cheng2011-02-211-0/+3
| | | | | | in a IT block. rdar://9030770 llvm-svn: 126159
* Revert r124611 - "Keep track of incoming argument's location while emitting ↵Devang Patel2011-02-211-5/+5
| | | | | | | | | | | LiveIns." In other words, do not keep track of argument's location. The debugger (gdb) is not prepared to see line table entries for arguments. For the debugger, "second" line table entry marks beginning of function body. This requires some coordination with debugger to get this working. - The debugger needs to be aware of prolog_end attribute attached with line table entries. - The compiler needs to accurately mark prolog_end in line table entries (at -O0 and at -O1+) llvm-svn: 126155
* Use explicit add_subdirectory's for LLVM target sublibraries insteadOscar Fuentes2011-02-201-0/+5
| | | | | | | | | of testing for its presence at cmake time. This way the build automatically regenerates the makefiles when a svn update brings in a new sublibrary. llvm-svn: 126068
* Avoid dangling else warnings.Joerg Sonnenberger2011-02-191-1/+2
| | | | llvm-svn: 126004
* Fix style and a typoBruno Cardoso Lopes2011-02-181-4/+4
| | | | llvm-svn: 125949
* Add assembly parsing support for "msr" and also fix its encoding. Also addBruno Cardoso Lopes2011-02-187-47/+169
| | | | | | testcases for the disassembler to make sure it still works for "msr". llvm-svn: 125948
* Triple::MinGW64 is deprecated and removed. We can use Triple::MinGW32 generally.NAKAMURA Takumi2011-02-171-1/+0
| | | | | | No one uses *-mingw64. mingw-w64 is represented as {i686|x86_64}-w64-mingw32. In llvm side, i686 and x64 can be treated as similar way. llvm-svn: 125747
* Some single precision VFP instructions may be executed on NEON pipeline, but ↵Evan Cheng2011-02-162-28/+160
| | | | | | not double precision ones. llvm-svn: 125624
* Teach ARMLoadStoreOptimizer to remove kill flags from merged instructions as ↵Jakob Stoklund Olesen2011-02-151-21/+15
| | | | | | | | | | | | | | | | | | | | | | | | | well. This is necessary to avoid a crash in certain tangled situations where a kill flag is first correctly moved to a merged instruction, and then needs to be moved again: STR %R0, a... STR %R0<kill>, b... First becomes: STR %R0, b... STM a, %R0<kill>, ... and then: STM a, %R0, ... STM b, %R0<kill>, ... We can now remove the kill flag from the merged STM when needed. 8960050. llvm-svn: 125591
* Spelling fix: consequtive -> consecutive.Duncan Sands2011-02-151-1/+1
| | | | llvm-svn: 125563
* Remove unused bitvectors that record ARM callee-saved registers.Bob Wilson2011-02-142-23/+0
| | | | llvm-svn: 125534
* A fail to match coprocessor number and register number must fail instead of ↵Bruno Cardoso Lopes2011-02-141-1/+0
| | | | | | assert. llvm-svn: 125521
* Fix encoding and add parsing support for the arm/thumb CPS instruction:Bruno Cardoso Lopes2011-02-1410-109/+276
| | | | | | | | | | | | - Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. llvm-svn: 125489
* Enhance ComputeMaskedBits to know that aligned frameindexesChris Lattner2011-02-131-40/+51
| | | | | | | | | | | | | | | | | have their low bits set to zero. This allows us to optimize out explicit stack alignment code like in stack-align.ll:test4 when it is redundant. Doing this causes the code generator to start turning FI+cst into FI|cst all over the place, which is general goodness (that is the canonical form) except that various pieces of the code generator don't handle OR aggressively. Fix this by introducing a new SelectionDAG::isBaseWithConstantOffset predicate, and using it in places that are looking for ADD(X,CST). The ARM backend in particular was missing a lot of addressing mode folding opportunities around OR. llvm-svn: 125470
* AsmMatcher custom operand parser failure enhancements.Jim Grosbach2011-02-123-23/+32
| | | | | | | | | | | Teach the AsmMatcher handling to distinguish between an error custom-parsing an operand and a failure to match. The former should propogate the error upwards, while the latter should continue attempting to parse with alternative matchers. Update the ARM asm parser accordingly. llvm-svn: 125426
* Implement sdiv & udiv for <4 x i16> and <8 x i8> NEON vector types.Nate Begeman2011-02-111-0/+182
| | | | | | This avoids moving each element to the integer register file and calling __divsi3 etc. on it. llvm-svn: 125402
* Fix buggy fcopysign lowering.Evan Cheng2011-02-111-5/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This define float @foo(float %x, float %y) nounwind readnone { entry: %0 = tail call float @copysignf(float %x, float %y) nounwind readnone ret float %0 } Was compiled to: vmov s0, r1 bic r0, r0, #-2147483648 vmov s1, r0 vcmpe.f32 s0, #0 vmrs apsr_nzcv, fpscr it lt vneglt.f32 s1, s1 vmov r0, s1 bx lr This fails to copy the sign of -0.0f because it's lost during the float to int conversion. Also, it's sub-optimal when the inputs are in GPR registers. Now it uses integer and + or operations when it's profitable. And it's correct! lsrs r1, r1, #31 bfi r0, r1, #31, #1 bx lr rdar://8984306 llvm-svn: 125357
* Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 ↵Owen Anderson2011-02-088-128/+86
| | | | | | (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. llvm-svn: 125127
* Temporary workaround for a bad bug introduced by r121082 which replacedEvan Cheng2011-02-082-8/+19
| | | | | | | | | | | | t2LDRpci with t2LDRi12. There are a couple of problems with this. 1. The encoding for the literal and immediate constant are different. Note bit 7 of the literal case is 'U' so it can be negative. 2. t2LDRi12 is now narrowed to tLDRpci before constant island pass is run. So we end up never using the Thumb2 instruction, which ends up creating a lot more constant islands. llvm-svn: 125074
* Add support for parsing dmb/dsb instructionsBruno Cardoso Lopes2011-02-073-0/+65
| | | | llvm-svn: 125055
* Remove the MCR asm parser hack and start using the custom target specific asmBruno Cardoso Lopes2011-02-072-31/+106
| | | | | | | | | | | | | | | | | | parsing of operands introduced in r125030. As a small note, besides using a more generic approach we can also have more descriptive output when debugging llvm-mc, example: mcr p7, #1, r5, c1, c1, #4 note: parsed instruction: ['mcr', <ARMCC::al>, <coprocessor number: 7>, 1, <register 73>, <coprocessor register: 1>, <coprocessor register: 1>, 4] llvm-svn: 125052
* ARM/MC/ELF Lowercase .cpu attributes in .s, but make them uppercase in .oJason W Kim2011-02-071-3/+3
| | | | llvm-svn: 125025
* Fix an obvious typo which caused an isel assertion. rdar://8964854.Evan Cheng2011-02-071-1/+1
| | | | llvm-svn: 125023
* Add codegen support for using post-increment NEON load/store instructions.Bob Wilson2011-02-073-145/+546
| | | | | | | | The vld1-lane, vld1-dup and vst1-lane instructions do not yet support using post-increment versions, but all the rest of the NEON load/store instructions should be handled now. llvm-svn: 125014
* Change VLD3/4 and VST3/4 for quad registers to not update the address register.Bob Wilson2011-02-073-65/+89
| | | | | | | | | | | | These operations are expanded to pairs of loads or stores, and the first one uses the address register update to produce the address for the second one. So far, the second load/store has also updated the address register, just for convenience, since that output has never been used. In anticipation of actually supporting post-increment updates for these operations, this changes the non-updating operations to use a non-updating load/store for the second instruction. llvm-svn: 125013
* Fix some NEON instruction itineraries.Bob Wilson2011-02-071-12/+16
| | | | llvm-svn: 125012
* Fix a comment: addrmode6 no longer includes the optional writeback flag.Bob Wilson2011-02-071-1/+1
| | | | llvm-svn: 125011
* Remove inaccurate comments: so_imm and t2_so_imm operands are not encodedBob Wilson2011-02-072-8/+2
| | | | | | until the instructions are emitted or printed. llvm-svn: 125010
* Move code for OffsetCompare struct closer to where it is used.Bob Wilson2011-02-071-11/+11
| | | | llvm-svn: 125009
* Rework some .ARM.attribute work for improved gcc compatibility.Jason W Kim2011-02-072-13/+84
| | | | | | | Unified EmitTextAttribute for both Asm and Obj emission (.cpu only) Added necessary cortex-A8 related attrs for codegen compat tests. llvm-svn: 124995
* Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps.Jason W Kim2011-02-045-10/+70
| | | | | | | | | | | | | | | | (yes, this is different from R_ARM_CALL) - Adds a new method getARMBranchTargetOpValue() which handles the necessary distinction between the conditional and unconditional br/bl needed for ARM/ELF At least for ARM mode, the needed fixup for conditional versus unconditional br/bl is identical, but the ARM docs and existing ARM tools expect this reloc type... Added a few FIXME's for future naming fixups in ARMInstrInfo.td llvm-svn: 124895
* MC/AsmParser: Add support for allowing the conversion process to fail (viaDaniel Dunbar2011-02-041-0/+2
| | | | | | custom conversion functions). llvm-svn: 124872
* Fix 80-column violations and whitespace.Bob Wilson2011-02-031-3/+3
| | | | llvm-svn: 124819
* Update comment to match my recent change.Bob Wilson2011-02-021-2/+2
| | | | llvm-svn: 124725
* Given a pair of floating point load and store, if there are no other uses ofEvan Cheng2011-02-022-2/+9
| | | | | | | | | | | | | | | | | | | the load, then it may be legal to transform the load and store to integer load and store of the same width. This is done if the target specified the transformation as profitable. e.g. On arm, this can transform: vldr.32 s0, [] vstr.32 s0, [] to ldr r12, [] str r12, [] rdar://8944252 llvm-svn: 124708
* PR9081: Split up LDM instruction with deprecated use of both LR and PC.Bob Wilson2011-02-011-2/+3
| | | | | | | This is completely untested but pretty straightforward, so hopefully I got it right. llvm-svn: 124694
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