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* ARM vector any_extends need to be selected to vmovl. <rdar://problem/10723651>Bob Wilson2012-01-201-0/+3
| | | | | | | | We have patterns for vector sext and zext operations but were missing anyext. Without those patterns, codegen will fail when the selection DAG has any_extend nodes. llvm-svn: 148568
* VST2 four-register w/ update pseudos for fixed/register update.Jim Grosbach2012-01-201-6/+15
| | | | | | rdar://10724489 llvm-svn: 148560
* NEON use vmov.i32 to splat some f32 values into vectors.Jim Grosbach2012-01-202-36/+41
| | | | | | | | | | | For bit patterns that aren't representable using the 8-bit floating point representation for vmov.f32, but are representable via vmov.i32, treat the .f32 syntax as an alias. Most importantly, this covers the case 'vmov.f32 Vd, #0.0'. rdar://10616677 llvm-svn: 148556
* Silence warnings about mixing enums.Benjamin Kramer2012-01-191-3/+2
| | | | llvm-svn: 148495
* Emit ARM EHABI unwinding instructions for 3 more Thumb instructions.Evgeniy Stepanov2012-01-191-0/+3
| | | | llvm-svn: 148473
* ARM assembly diagnostic caret in better position for FPImm.Jim Grosbach2012-01-191-3/+4
| | | | llvm-svn: 148459
* Thumb2 relaxation for tADR to t2ADR.Jim Grosbach2012-01-191-0/+2
| | | | llvm-svn: 148456
* Add comment and fix range check in condition.Jim Grosbach2012-01-191-1/+3
| | | | llvm-svn: 148455
* - Slight change to finalizeBundle() interface. LastMI is not exclusive (pointingEvan Cheng2012-01-191-1/+2
| | | | | | | | | | | to instruction right after the last instruction in the bundle. - Add a finalizeBundle() variant that doesn't specify LastMI. Instead, the code will find the last instruction in the bundle by following the 'InsideBundle' marker. This is useful in case bundles are formed early (i.e. during MI scheduling) but finalized later (i.e. after register allocator has finished rewriting virtual registers with physical registers). llvm-svn: 148444
* Rename Finalizebundle to finalizeBundle to conform to coding guideline.Evan Cheng2012-01-191-1/+1
| | | | llvm-svn: 148440
* Ignore register mask operands when lowering instructions to MC.Jakob Stoklund Olesen2012-01-181-0/+3
| | | | | | | This is similar to implicit register operands. MC doesn't understand register liveness and call clobbers. llvm-svn: 148437
* Thumb2 alternate syntax for LDR(literal) and friends.Jim Grosbach2012-01-183-0/+69
| | | | | | | | Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]". rdar://10250964 llvm-svn: 148432
* Replace FIXME with explanatory comment.Jim Grosbach2012-01-181-1/+2
| | | | llvm-svn: 148427
* Thumb2 relaxation for LDR(literal).Jim Grosbach2012-01-181-9/+20
| | | | | | | | | If the fixup is out of range for the Thumb1 instruction, relax it to the Thumb2 encoding instead. rdar://10711829 llvm-svn: 148424
* Rename pattern for clarity.Jim Grosbach2012-01-181-4/+3
| | | | llvm-svn: 148422
* Tidy up. MCAsmBackend naming conventions.Jim Grosbach2012-01-181-11/+11
| | | | llvm-svn: 148400
* Thumb2 load/store fixups don't set the thumb bit.Jim Grosbach2012-01-181-4/+8
| | | | | | | | | | Load/store instructions w/ a fixup to be relative a function marked as thumb don't use the low bit to specify thumb vs. non-thumb like interworking branches do, so don't set it when dealing with those fixups. rdar://10348687. llvm-svn: 148366
* Move some ARM specific MCAssmebler bits into the ARMAsmBackend.Jim Grosbach2012-01-181-0/+15
| | | | llvm-svn: 148364
* Add a CoveredBySubRegs property to Register descriptions.Jakob Stoklund Olesen2012-01-181-0/+2
| | | | | | | | | | | | | | | | When set, this bit indicates that a register is completely defined by the value of its sub-registers. Use the CoveredBySubRegs property to infer which super-registers are call-preserved given a list of callee-saved registers. For example, the ARM registers D8-D15 are callee-saved. This now automatically implies that Q4-Q7 are call-preserved. Conversely, Win64 callees save XMM6-XMM15, but the corresponding YMM6-YMM15 registers are not call-preserved because they are not fully defined by their sub-registers. llvm-svn: 148363
* Implement ARMBaseRegisterInfo::getCallPreservedMask().Jakob Stoklund Olesen2012-01-173-19/+17
| | | | | | Move ARM callee-saved lists into ARMCallingConv.td. llvm-svn: 148357
* Removing unused default switch cases in switches over enums that already ↵David Blaikie2012-01-162-7/+1
| | | | | | | | account for all enumeration values explicitly. (This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them) llvm-svn: 148262
* Refactor variables unused under non-assert builds (& remove two entirely ↵David Blaikie2012-01-161-2/+2
| | | | | | unused variables). llvm-svn: 148230
* Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through ↵Benjamin Kramer2012-01-151-20/+12
| | | | | | CodeGen. llvm-svn: 148218
* After r147827 and r147902, it's now possible for unallocatable registers to beEvan Cheng2012-01-141-0/+5
| | | | | | | | | | | | | | | | | | | live across BBs before register allocation. This miscompiled 197.parser when a cmp + b are optimized to a cbnz instruction even though the CPSR def is live-in a successor. cbnz r6, LBB89_12 ... LBB89_12: ble LBB89_1 The fix consists of two parts. 1) Teach LiveVariables that some unallocatable registers might be liveouts so don't mark their last use as kill if they are. 2) ARM constantpool island pass shouldn't form cbz / cbnz if the conditional branch does not kill CPSR. rdar://10676853 llvm-svn: 148168
* Use RegisterTuples to generate pseudo-registers.Jakob Stoklund Olesen2012-01-134-45/+51
| | | | | | | | | | The QQ and QQQQ registers are not 'real', they are pseudo-registers used to model some vld and vst instructions. This makes the call clobber lists longer, but I intend to get rid of those soon. llvm-svn: 148151
* Fix assert.Eric Christopher2012-01-111-2/+2
| | | | llvm-svn: 147966
* ARM Ld/St Optimizer fix.Andrew Trick2012-01-111-3/+4
| | | | | | | | Allow LDRD to be formed from pairs with different LDR encodings. This was the original intention of the pass. Somewhere along the way, the LDR opcodes were refined which broke the optimization. We really don't care what the original opcodes are as long as they both map to the same LDRD and the immediate still fits. Fixes rdar://10435045 ARMLoadStoreOptimization cannot handle mixed LDRi8/LDRi12 llvm-svn: 147922
* Consider unknown alignment caused by OptimizeThumb2Instructions().Jakob Stoklund Olesen2012-01-101-4/+25
| | | | | | | | | | | | | | | | | | | | This function runs after all constant islands have been placed, and may shrink some instructions to their 2-byte forms. This can actually cause some constant pool entries to move out of range because of growing alignment padding. Treat instructions that may be shrunk the same as inline asm - they erode the known alignment bits. Also reinstate an old assertion in verify(). It is correct now that basic block offsets include alignments. Add a single large test case that will hopefully exercise many parts of the constant island pass. <rdar://problem/10670199> llvm-svn: 147885
* ARM updating VST2 pseudo-lowering fixed vs. register update.Jim Grosbach2012-01-103-8/+8
| | | | | | rdar://10663487 llvm-svn: 147876
* Move default case for covered enum outside of switch.Richard Smith2012-01-101-1/+1
| | | | llvm-svn: 147870
* Fix a -Wreturn-type warning in g++.Richard Smith2012-01-101-0/+1
| | | | llvm-svn: 147867
* Remove unnecessary default cases in switches that cover all enum values.David Blaikie2012-01-103-4/+0
| | | | llvm-svn: 147855
* Accurately model hardware alignment rounding.Jakob Stoklund Olesen2012-01-101-21/+56
| | | | | | | | | | | | | | | | | | | On Thumb, the displacement computation hardware uses the address of the current instruction rouned down to a multiple of 4. Include this rounding in the UserOffset we compute for each instruction. When inline asm is present, the instruction alignment may not be known. Constrain the maximum displacement instead in that case. This makes it possible for CreateNewWater() and OffsetIsInRange() to agree about the valid displacements. When they disagree, infinite looping happens. As always, test cases for this stuff are insane. <rdar://problem/10660175> llvm-svn: 147825
* Catch runaway ARMConstantIslandPass even in -Asserts builds.Jakob Stoklund Olesen2012-01-091-2/+2
| | | | | | | | | The pass is prone to looping, and it is better to crash than loop forever, even in a -Asserts build. <rdar://problem/10660175> llvm-svn: 147806
* Don't forget to transfer implicit uses of return instruction.Evan Cheng2012-01-081-2/+5
| | | | llvm-svn: 147752
* Match SelectionDAG logic for enabling movt.Jakob Stoklund Olesen2012-01-072-2/+7
| | | | | | Darwin doesn't do static, and ELF targets only support static. llvm-svn: 147740
* Remove VectorExtras. This unused helper was written for a type of API that ↵Benjamin Kramer2012-01-071-1/+0
| | | | | | is discouraged now. llvm-svn: 147738
* Use getRegForValue() to materialize the address of ARM globals.Jakob Stoklund Olesen2012-01-071-10/+0
| | | | | | | | | This enables basic local CSE, giving us 20% smaller code for consumer-typeset in -O0 builds. <rdar://problem/10658692> llvm-svn: 147720
* Copy implicit defs (e.g. r0) when changing tBX_RET to tPOP_RET. This bug isEvan Cheng2012-01-071-0/+1
| | | | | | | exposed with an upcoming change will would delete the copy to return register because there is no use! It's amazing anything works. llvm-svn: 147715
* Use movw+movt in ARMFastISel::ARMMaterializeGV.Jakob Stoklund Olesen2012-01-071-29/+50
| | | | | | | | | | | | | This eliminates a lot of constant pool entries for -O0 builds of code with many global variable accesses. This speeds up -O0 codegen of consumer-typeset by 2x because the constant island pass no longer has to look at thousands of constant pool entries. <rdar://problem/10629774> llvm-svn: 147712
* Enable aligned NEON spilling by default.Jakob Stoklund Olesen2012-01-061-1/+1
| | | | | | Experiments show this to be a small speedup for modern ARM cores. llvm-svn: 147689
* Abort AdjustBBOffsetsAfter early when possible.Jakob Stoklund Olesen2012-01-061-2/+10
| | | | llvm-svn: 147685
* Reapply r146997, "Heed spill slot alignment on ARM."Jakob Stoklund Olesen2012-01-052-3/+4
| | | | | | | | | | | | Now that canRealignStack() understands frozen reserved registers, it is safe to use it for aligned spill instructions. It will only return true if the registers reserved at the beginning of register allocation allow for dynamic stack realignment. <rdar://problem/10625436> llvm-svn: 147579
* Avoid reserving an ARM base pointer during register allocation.Jakob Stoklund Olesen2012-01-051-2/+17
| | | | | | | | | | | | | | | | | Once register allocation has started the reserved registers are frozen. Fix the ARM canRealignStack() hook to respect the frozen register state. Now the hook returns false if register allocation was started with frame pointer elimination enabled. It also returns false if register allocation started without a reserved base pointer, and stack realignment would require a base pointer. This bug was breaking oggenc on armv6. No test case, an upcoming patch will use this functionality to realign the stack for spill slots when possible. llvm-svn: 147578
* Fix more places which should be checking for iOS, not darwin.Evan Cheng2012-01-043-18/+18
| | | | llvm-svn: 147513
* Revert r146997, "Heed spill slot alignment on ARM."Jakob Stoklund Olesen2012-01-032-4/+3
| | | | | | | | | This patch caused a miscompilation of oggenc because a frame pointer was suddenly needed halfway through register allocation. <rdar://problem/10625436> llvm-svn: 147487
* Fix malformed assert.Matt Beaumont-Gay2012-01-031-1/+1
| | | | | | | | If anybody has strong feelings about 'default: assert(0 && "blah")' vs 'default: llvm_unreachable("blah")', feel free to regularize the instances of each in this file. llvm-svn: 147459
* Fix Comments.Jakob Stoklund Olesen2011-12-241-3/+3
| | | | llvm-svn: 147238
* Experimental support for aligned NEON spills.Jakob Stoklund Olesen2011-12-233-13/+377
| | | | | | | | | | | | | ARM targets with NEON units have access to aligned vector loads and stores that are potentially faster than unaligned operations. Add support for spilling the callee-saved NEON registers to an aligned stack area using 16-byte aligned NEON loads and store. This feature is off by default, controlled by an -align-neon-spills command line option. llvm-svn: 147211
* Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138>Bob Wilson2011-12-224-7/+23
| | | | | | | | | | | My change r146949 added register clobbers to the eh_sjlj_dispatchsetup pseudo instruction, but on Thumb1 some of those registers cannot be used. This caused massive failures on the testsuite when compiling for Thumb1. While fixing that, I noticed that the eh_sjlj_setjmp instruction has a "nofp" variant, and I realized that dispatchsetup needs the same thing, so I have added that as well. llvm-svn: 147204
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