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* Remove VLD1q and VST1q for reloading and spilling Q registers. Just use ↵Evan Cheng2010-05-072-32/+23
| | | | | | VLD1q64 / VST1q64 and reference sub-registers. llvm-svn: 103218
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-067-18/+17
| | | | | | doesn't have to guess. llvm-svn: 103194
* Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.Evan Cheng2010-05-066-26/+38
| | | | llvm-svn: 103193
* Add a missing break statement to fix unintentional fall-throughBob Wilson2010-05-061-4/+3
| | | | | | (replacing the previous patch for the same issue). llvm-svn: 103183
* Fix unintentional fallthrough. Patch by Edmund Grimley-Evans ↵Jim Grosbach2010-05-061-1/+2
| | | | | | <Edmund.Grimley-Evans@arm.com> llvm-svn: 103181
* Fix "warning: extra ';' inside a struct or union" when building llvm with clangShantonu Sen2010-05-061-2/+2
| | | | llvm-svn: 103179
* Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a ↵Evan Cheng2010-05-065-23/+146
| | | | | | coalescer bug that's fixed by 103170. llvm-svn: 103172
* Revert r103157, which broke test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll.Dan Gohman2010-05-061-4/+2
| | | | llvm-svn: 103163
* Revert r103156 since it was breaking the build bots.Eric Christopher2010-05-065-142/+21
| | | | | | | | | | | Reverse-merging r103156 into '.': U lib/Target/ARM/ARMInstrNEON.td U lib/Target/ARM/ARMRegisterInfo.h U lib/Target/ARM/ARMBaseRegisterInfo.cpp U lib/Target/ARM/ARMBaseInstrInfo.cpp U lib/Target/ARM/ARMRegisterInfo.td llvm-svn: 103159
* Fix an obvious bug in isMoveInstr. It needs to return sub-register indices.Evan Cheng2010-05-061-2/+4
| | | | llvm-svn: 103157
* Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q ↵Evan Cheng2010-05-065-21/+142
| | | | | | registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them. llvm-svn: 103156
* Cosmetic changes.Evan Cheng2010-05-061-7/+7
| | | | llvm-svn: 103155
* storeRegToStackSlot has forgotten about QPR_8 register class.Evan Cheng2010-05-061-1/+2
| | | | llvm-svn: 103154
* Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/packJim Grosbach2010-05-056-24/+38
| | | | | | | instructions to subtarget features and update tests to reflect. PR5717. llvm-svn: 103136
* Do not pre-allocate references of D registers pairs if they are extracted ↵Evan Cheng2010-05-051-8/+28
| | | | | | from the same Q register and are in the right order. llvm-svn: 103124
* Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch byJim Grosbach2010-05-056-20/+49
| | | | | | | | | Jordy <snhjordy@gmail.com>. Followup patches will add some tests and adjust to use Subtarget features for the instructions. llvm-svn: 103119
* Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE.Evan Cheng2010-05-053-4/+38
| | | | llvm-svn: 103104
* With -neon-reg-sequence, models forming a Q register from a pair of ↵Evan Cheng2010-05-041-2/+11
| | | | | | consecutive D registers as a REG_SEQUENCE. llvm-svn: 103047
* Do not pre-allocate for registers which form a REG_SEQUENCE.Evan Cheng2010-05-041-0/+28
| | | | llvm-svn: 103041
* rdar://7937137 - dbg values not being handled in thumb1 version ofJim Grosbach2010-05-041-0/+7
| | | | | | eliminateFrameIndex(), leading to llvm_unreachable() assertion failure. llvm-svn: 102980
* Get rid of the EdgeMapping map. Instead, just check for BasicBlockDan Gohman2010-05-012-9/+5
| | | | | | changes before doing phi lowering for switches. llvm-svn: 102809
* Frame index can be negative.Evan Cheng2010-04-292-2/+2
| | | | llvm-svn: 102577
* Add sizes non-floating point versions for the eh sjlj intrinsic expansions.Jim Grosbach2010-04-281-1/+2
| | | | | | rdar://7895451 llvm-svn: 102526
* Handle register-to-register copies within the tGPR class.Bob Wilson2010-04-261-12/+16
| | | | | | Radar 7896289 llvm-svn: 102396
* Handle target-specific form of DBG_VALUE in AsmPrinter.Dale Johannesen2010-04-261-0/+19
| | | | llvm-svn: 102373
* Add ARM specific emitFrameIndexDebugValue.Evan Cheng2010-04-263-0/+23
| | | | llvm-svn: 102324
* Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfieldJim Grosbach2010-04-221-6/+40
| | | | | | extraction. This fixes PR5998. llvm-svn: 102144
* Modified some assert() msg strings; no other functionality change.Johnny Chen2010-04-211-14/+14
| | | | llvm-svn: 102008
* Implement -disable-non-leaf-fp-elim which disable frame pointer eliminationEvan Cheng2010-04-211-2/+2
| | | | | | | optimization for non-leaf functions. This will be hooked up to gcc's -momit-leaf-frame-pointer option. rdar://7886181 llvm-svn: 101984
* Thumb instructions which have reglist operands at the end and predicate operandsJohnny Chen2010-04-213-14/+68
| | | | | | | | before reglist were not properly handled with respect to IT Block. Fix that by creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those instructions for disassembly. Add a test case. llvm-svn: 101974
* Better error-handling of getBitFieldInvMask() where msb < lsb (encoding error),Johnny Chen2010-04-201-6/+14
| | | | | | instead of just asserting. llvm-svn: 101942
* For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if ↵Johnny Chen2010-04-201-5/+5
| | | | | | | | | Rn(Inst{19-16})=='1111', transform the Opcode to the corresponding t2LDR*pci counterpart. Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT llvm-svn: 101915
* Better error-handling for DisassembleThumb2DPModImm() with 2-reg operands whereJohnny Chen2010-04-201-1/+4
| | | | | | d==15 is considered illegal. Return false instead of assert(). llvm-svn: 101852
* More IT instruction error-handling improvements from fuzzing.Johnny Chen2010-04-201-3/+17
| | | | llvm-svn: 101839
* Better error handling of invalid IT mask '0000', instead of just asserting.Johnny Chen2010-04-193-5/+11
| | | | llvm-svn: 101827
* According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1Johnny Chen2010-04-191-8/+13
| | | | | | | | | | Pseudocode details of conditional, Condition bits '111x' indicate the instruction is always executed. That is, '1111' is a leagl condition field value, which is now mapped to ARMCC::AL. Also add a test case for condition field '1111'. llvm-svn: 101817
* Better error-handling for DisassembleThumb2DPSoReg() where the 3-reg operandJohnny Chen2010-04-191-3/+6
| | | | | | | | instructions should have Rd (Inst{11-8}) != 0b1111. Ref: A6.3 32-bit Thumb instruction encoding A6.3.11 Data-processing (shifted register) llvm-svn: 101788
* ARM disassembler did not react to recent changes to the NEON instruction table.Johnny Chen2010-04-191-10/+22
| | | | | | VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now. llvm-svn: 101784
* Make processor FUs unique for given itinerary. This extends the limit of 32Anton Korobeynikov2010-04-184-838/+846
| | | | | | | FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
* Fix -Wcast-qual warnings.Dan Gohman2010-04-171-4/+5
| | | | llvm-svn: 101655
* Add const qualifiers to TargetLoweringObjectFile usage.Dan Gohman2010-04-171-4/+5
| | | | llvm-svn: 101640
* Use const qualifiers with TargetLowering. This eliminates severalDan Gohman2010-04-174-61/+72
| | | | | | | | | | | | | const_casts, and it reinforces the design of the Target classes being immutable. SelectionDAGISel::IsLegalToFold is now a static member function, because PIC16 uses it in an unconventional way. There is more room for API cleanup here. And PIC16's AsmPrinter no longer uses TargetLowering. llvm-svn: 101635
* Move per-function state out of TargetLowering subclasses and intoDan Gohman2010-04-173-15/+26
| | | | | | MachineFunctionInfo subclasses. llvm-svn: 101634
* Revise my previous change to ExpandBIT_CONVERT. I hadn't realized that thisBob Wilson2010-04-171-12/+22
| | | | | | | | | may be called when either the source or destination type is i64, and my change also hadn't fixed the most obvious problem -- assuming that i64 will only be bitconverted to f64, ignoring the various vector types. Radar 7873160. llvm-svn: 101615
* Cast to (uint64_t) instead of relying on the "ul" suffix.Johnny Chen2010-04-161-1/+1
| | | | llvm-svn: 101573
* Add skeleton target-specific SelectionDAGInfo files.Dan Gohman2010-04-163-0/+52
| | | | llvm-svn: 101564
* Fixed logic error. Should check Builder for validity before calling SetSessionJohnny Chen2010-04-161-3/+2
| | | | | | on it. llvm-svn: 101563
* Fixed a bug in DisassembleN1RegModImmFrm() where a break stmt was missing for aJohnny Chen2010-04-163-5/+26
| | | | | | | | | | case. Also, the 0xFF hex literal involved in the shift for ESize64 should be suffixed "ul" to preserve the shift result. Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand(). llvm-svn: 101557
* In the same spirit of r101524, which removed the assert() from ↵Johnny Chen2010-04-162-2/+0
| | | | | | | | printAddrMode2OffsetOperand(), this patch removes the assert() from printAddrMode3OffsetOperand() and adds a test case. llvm-svn: 101529
* Multiclass LdStCop was using pre-UAL syntax LDC<c>L for the L fragment. ChangedJohnny Chen2010-04-161-4/+4
| | | | | | | | | to the UAL syntax of LDCL<c>, instead. Add a test case for this change which also tests the removal of assert() from printAddrMode2OffsetOperand(). llvm-svn: 101527
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