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* [ARM] Constrain some register classes in EmitAtomicBinary64 so thatJoey Gouly2013-08-221-0/+4
| | | | | | we pass these tests with -verify-machineinstrs. llvm-svn: 189006
* Fix ARM FastISel PIC function call.Logan Chien2013-08-221-2/+9
| | | | | | | The function call to external function should come with PLT relocation type if the PIC relocation model is used. llvm-svn: 189002
* ARM: use TableGen patterns to select CMOV operations.Tim Northover2013-08-227-326/+137
| | | | | | | | | | | | Back in the mists of time (2008), it seems TableGen couldn't handle the patterns necessary to match ARM's CMOV node that we convert select operations to, so we wrote a lot of fairly hairy C++ to do it for us. TableGen can deal with it now: there were a few minor differences to CodeGen (see tests), but nothing obviously worse that I could see, so we should probably address anything that *does* come up in a localised manner. llvm-svn: 188995
* ARM: respect tied 64-bit inlineasm operands when printingTim Northover2013-08-221-0/+17
| | | | | | | The code for 'Q' and 'R' operand modifiers needs to look through tied operands to discover the register class. llvm-svn: 188990
* ARM: R9 is not safe to use for tcGPR.Jim Grosbach2013-08-221-1/+1
| | | | | | | | | Indirect tail-calls shouldn't use R9 for the branch destination, as it's not reliably a call-clobbered register. rdar://14793425 llvm-svn: 188967
* Make "mov" work for all Thumb2 MOV encodingsMihai Popa2013-08-213-0/+17
| | | | | | | According to the ARM specification, "mov" is a valid mnemonic for all Thumb2 MOV encodings. To achieve this, the patch adds one instruction alias with a special range condition to avoid collision with the Thumb1 MOV. llvm-svn: 188901
* ARM: Fix fast-isel copy/paste-o.Jim Grosbach2013-08-201-1/+1
| | | | | | | | | | | | Update testcase to be more careful about checking register values. While regexes are general goodness for these sorts of testcases, in this example, the registers are constrained by the calling convention, so we can and should check their explicit values. rdar://14779513 llvm-svn: 188819
* ARM: implement some simple f64 materializations.Tim Northover2013-08-201-10/+40
| | | | | | | | Previously we used a const-pool load for virtually all 64-bit floating values. Actually, we can get quite a few common values (including 0.0, 1.0) via "vmov" instructions of one stripe or another. llvm-svn: 188773
* Thumb2 add immediate alias for SPMihai Popa2013-08-191-1/+2
| | | | | | | | The Thumb2 add immediate is in fact defined for SP. The manual is misleading as it points to a different section for add immediate with SP, however the encoding is the same as for add immediate with register only with the SP operand hard coded. As such add immediate with SP and add immediate with register can safely be treated as the same instruction. All the patch does is adjust a register constraint on an instruction alias. llvm-svn: 188676
* ARM: make sure we keep inline asm operands tied.Tim Northover2013-08-181-1/+4
| | | | | | | | When patching inlineasm nodes to use GPRPair for 64-bit values, we were dropping the information that two operands were tied, which effectively broke the live-interval of vregs affected. llvm-svn: 188643
* ARM: Properly constrain comparison fastisel register classes.Jim Grosbach2013-08-161-5/+12
| | | | | | | | Ongoing 'make the verifier happy' improvements to ARM fast-isel. rdar://12594152 llvm-svn: 188595
* ARM: Fast-isel register class constrain for extends.Jim Grosbach2013-08-161-0/+1
| | | | | | | | | | Properly constrain the operand register class for instructions used in [sz]ext expansion. Update more tests to use the verifier now that we're getting the register classes correct. rdar://12594152 llvm-svn: 188594
* ARM: Fix more fast-isel verifier failures.Jim Grosbach2013-08-161-0/+43
| | | | | | | | | | | | | Teach the generic instruction selection helper functions to constrain the register classes of their input operands. For non-physical register references, the generic code needs to be careful not to mess that up when replacing references to result registers. As the comment indicates for MachineRegisterInfo::replaceRegWith(), it's important to call constrainRegClass() first. rdar://12594152 llvm-svn: 188593
* ARM: Clean up fast-isel machine verifier errors.Jim Grosbach2013-08-161-1/+1
| | | | | | | | | | | | | Lots of machine verifier errors result from using a plain GPR regclass for incoming argument copies. A more restrictive rGPR class is more appropriate since it more accurately represents what's happening, plus it lines up better with isel later on so the verifier is happier. Reduces the number of ARM fast-isel tests not running with the verifier enabled by over half. rdar://12594152 llvm-svn: 188592
* When initializing the PIC global base register on ARM/ELF add pc to fix the ↵Benjamin Kramer2013-08-161-0/+4
| | | | | | | | | | address. This unbreaks PIC with fast isel on ELF targets (PR16717). The output matches what GCC and SDag do for PIC but may not cover all of the many flavors of PIC that exist. llvm-svn: 188551
* Add support for Thumb2 literal loads with negative zero offsetMihai Popa2013-08-162-4/+4
| | | | | | | | Thumb2 literal loads use an offset encoding which allows for negative zero. This fixes parsing and encoding so that #-0 is correctly processed. The parser represents #-0 as INT32_MIN. llvm-svn: 188549
* Fix Thumb2 aliasing complementary instructions taking modified immediatesMihai Popa2013-08-162-5/+6
| | | | | | | | | | | | | | | | | | | | | There are many Thumb instructions which take 12-bit immediates encoded in a special 8-byte value + 4-byte rotator form. Not all numbers are represented, and it's legal to transform an assembly instruction to be able to encode the immediate. For example: AND and BIC are complementary instructions; one can switch the AND to a BIC as long as the immediate is complemented. The intent is to switch one instruction into its complementary one when the immediate cannot be encoded in the form requested in the original assembly and when the complementary immediate is encodable. The patch addresses two issues: 1. definition of t2SOImmNot immediate - it has to check that the orignal value is not encoded naturally 2. t2AND and t2BIC instruction aliases which should use the Thumb2 SOImm operand rather than the ARM one. llvm-svn: 188548
* make arm-use-movt available for all ARMRenato Golin2013-08-151-3/+3
| | | | | | | | | | | | | Before this patch this flag is IOS specific, but is also useful for bare project like bootloaders / kernels etc, since movw / movt prevents simple relocation. Therefore make this flag more commonly available. note: this patch depends on a similiar rename in clang Patch by Jeroen Hofstee. llvm-svn: 188487
* make arm-reserve-r9 available for all ARMRenato Golin2013-08-151-2/+3
| | | | | | | | | | | r9 is defined as a platform-specific register in the ARM EABI. It can be reserved for a special purpose or be used as a general purpose register. Add support for reserving r9 for all ARM, while leaving the IOS usage unchanged. Patch by Jeroen Hofstee. llvm-svn: 188485
* This fixes three issues related to Thumb literal loads:Mihai Popa2013-08-153-7/+4
| | | | | | | | | 1. The offset range for Thumb1 PC relative loads is [0..1020] and not [-1024..1020] 2. Thumb2 PC relative loads may define the PC, so the restriction placed on target register is removed 3. Removes unneeded alias between "ldr.n" and t1LDRpci. ".n" is actually stripped by both tablegen and the ASM parser, so this alias rule really does nothing llvm-svn: 188466
* Replace getValueType().getSimpleVT() with getSimpleValueType(). Also remove ↵Craig Topper2013-08-151-1/+1
| | | | | | one weird cast from MVT->EVT just to call getSimpleVT(). llvm-svn: 188441
* Let t2LDRBi8 and t2LDRBi12 have same Base PointerRenato Golin2013-08-141-1/+14
| | | | | | | | | | | | | | When determining if two different loads are from the same base address, this patch allows one load to use a t2LDRi8 address mode and another to use a t2LDRi12 address mode. The current implementation is very conservative and this allows the case of differing Thumb2 byte loads to be considered. Allowing these differing modes instead of forcing the exact same opcode is useful for situations where one opcodes loads from a base address+1 and a second opcode loads for a base address-1. Patch by Daniel Stewart. llvm-svn: 188385
* ARMv8: SWP and SWPB are obsoleted on ARMv8.Joey Gouly2013-08-131-2/+6
| | | | llvm-svn: 188288
* Fix signed overflow in when computing encodings for ADR instructionsMihai Popa2013-08-131-1/+1
| | | | llvm-svn: 188268
* Add a overload to CostTable which allows it to infer the size of the table.Benjamin Kramer2013-08-091-34/+27
| | | | | | | | Use it to avoid repeating ourselves too often. Also store MVT::SimpleValueType in the TTI tables so they can be statically initialized, MVT's constructors create bloated initialization code otherwise. llvm-svn: 188095
* This fixes the Thumb2 CPS assembly syntax.Mihai Popa2013-08-091-1/+5
| | | | | | | | | | | | | | In Thumb1, only one variant is supported: CPS{effect} {flags} Thumb2 supports three: CPS{effect}.W {flags} CPS{effect} {flags} {mode} CPS {mode} Canonically, .W should be used only when ambiguity is present between encodings of different width. The wide suffix is still accepted for the latter two forms via aliases. llvm-svn: 188071
* Fix assembling of Thumb2 branch instructions.Mihai Popa2013-08-094-10/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The long encoding for Thumb2 unconditional branches is broken. Additionally, there is no range checking for target operands; as such for instructions originating in assembly code, only short Thumb encodings are generated, regardless of the bitsize needed for the offset. Adding range checking is non trivial due to the representation of Thumb branch instructions. There is no true difference between conditional and unconditional branches in terms of operands and syntax - even unconditional branches have a predicate which is expected to match that of the IT block they are in. Yet, the encodings and the permitted size of the offset differ. Due to this, for any mnemonic there are really 4 encodings to choose for. The problem cannot be handled in the parser alone or by manipulating td files. Because the parser builds first a set of match candidates and then checks them one by one, whatever tablegen-only solution might be found will ultimately be dependent of the parser's evaluation order. What's worse is that due to the fact that all branches have the same syntax and the same kinds of operands, that order is governed by the lexicographical ordering of the names of operand classes... To circumvent all this, any necessary disambiguation is added to the instruction validation pass. llvm-svn: 188067
* Remove the now redundant FeatureFP16 from the Cortex-A15 feature list. It ↵Silviu Baranga2013-08-081-1/+1
| | | | | | was made redundant when FeatureVFP4 was added which implies FP16. llvm-svn: 187985
* The name "tCDP" isn't used anywhere else in the source code, so renaming it ↵Mihai Popa2013-08-081-1/+1
| | | | | | | | | | for consistency doesn't cause any problems. This is the only Thumb2 instruction defined with "t" prefix; all other Thumb2 instructions have "t2" prefix (e.g. "t2CDP2" which is defined immediately afterwards). Patch by Artyom Skrobov. llvm-svn: 187973
* This corrects creation of operands for t2PLDW. It also removes the ↵Mihai Popa2013-08-062-25/+24
| | | | | | | | definition of t2PLDWpci, as pldw does not have a literal variant (i.e. pc relative version) llvm-svn: 187804
* Support APSR_nzcv as operand for Thumb2 mrc. Deprecate pre-UAL syntax (pc ↵Mihai Popa2013-08-062-5/+5
| | | | | | instead of apsr_nzcv) llvm-svn: 187803
* ARM: implement allowTruncateForTailCallTim Northover2013-08-062-0/+18
| | | | | | | Now that it's in place, it seems silly not to let ARM make use of the extra tail call opportunities. llvm-svn: 187795
* Target/*/CMakeLists.txt: Add the dependency to CommonTableGen explicitly for ↵NAKAMURA Takumi2013-08-061-1/+1
| | | | | | | | | each corresponding CodeGen. Without explicit dependencies, both per-file action and in-CommonTableGen action could run in parallel. It races to emit *.inc files simultaneously. llvm-svn: 187780
* ARMAsmParser: Plug a leak.Benjamin Kramer2013-08-031-3/+11
| | | | | | Using an object to do the cleanup may look like overkill, but it's safer and nicer than putting deletes everywhere. llvm-svn: 187696
* Add a missing 'return' statement.Joey Gouly2013-08-021-0/+1
| | | | llvm-svn: 187671
* [ARMv8] Add an assembler warning for the deprecated 'setend' instruction.Joey Gouly2013-08-021-0/+12
| | | | llvm-svn: 187666
* Fixes ARM LNT bot from SLP change in O3Renato Golin2013-08-021-6/+8
| | | | | | | | | | | | This patch fixes the multiple breakages on ARM test-suite after the SLP vectorizer was introduced by default on O3. The problem was an illegal vector type on ARMTTI::getCmpSelInstrCost() <3 x i1> which is not simple. The guard protects this code from breaking (cause of the problems) but doesn't fix the issue that is generating the odd vector in the first place, which also needs to be investigated. llvm-svn: 187658
* Use function attributes to indicate that we don't want to realign the stack.Bill Wendling2013-08-011-1/+1
| | | | | | | | Function attributes are the future! So just query whether we want to realign the stack directly from the function instead of through a random target options structure. llvm-svn: 187618
* Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.Kevin Enderby2013-07-312-0/+30
| | | | | | | | | | | While the .td entry is nice and all, it takes a pretty gross hack in ARMAsmParser::ParseInstruction() because of handling of other "subs" instructions to get it to match. Ran it by Jim Grosbach and he said it was about what he expected to make this work given the existing code. rdar://14214063 llvm-svn: 187530
* [ARM] check bitwidth in PerformORCombineSaleem Abdulrasool2013-07-301-14/+21
| | | | | | | | | | | | | When simplifying a (or (and B A) (and C ~A)) to a (VBSL A B C) ensure that the bitwidth of the second operands to both ands match before comparing the negation of the values. Split the check of the value of the second operands to the ands. Move the cast and variable declaration slightly higher to make it slightly easier to follow. Bug-Id: 16700 Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org> llvm-svn: 187404
* Allow generation of vmla.f32 instructions when targeting Cortex-A15. The ↵Silviu Baranga2013-07-294-4/+6
| | | | | | patch also adds the VFP4 feature to Cortex-A15 and fixes the DontUseFusedMAC predicate so that we can still generate vmla.f32 instructions on non-darwin targets with VFP4. llvm-svn: 187349
* Create a constant pool symbol for the GOT in the ARMCGBR the same way weChandler Carruth2013-07-271-7/+8
| | | | | | | | | | | | | | do in the SDag when lowering references to the GOT: use ARMConstantPoolSymbol rather than creating a dummy global variable. The computation of the alignment still feels weird (it uses IR types and datalayout) but it preserves the exact previous behavior. This change fixes the memory leak of the global variable detected on the valgrind leak checking bot. Thanks to Benjamin Kramer for pointing me at ARMConstantPoolSymbol to handle this use case. llvm-svn: 187303
* Fix yet another memory leak found by the vg-leak bot. Folks (includingChandler Carruth2013-07-271-2/+6
| | | | | | | | | | | | | | | | me) should start watching this bot more as its catching lots of bugs. The fix here is to not construct the global if we aren't going to need it. That's cheaper anyways, and globals have highly predictable types in practice. I've added an assert to catch skew between our manual testing of the type and the actual type just for paranoia's sake. Note that this pattern is actually fine in most globals because when you build a global with a module it automatically is moved to be owned by that module. But here, we're in isel and don't really want to do that. The solution of not creating a global is simpler anyways. llvm-svn: 187302
* [ARM][ISel] Improve the lowering of vector loads.Quentin Colombet2013-07-231-1/+3
| | | | | | | | | | | | | | | | When vectors are built from a single value, the ARM lowering issues a scalar_to_vector node. This node is then always morphed into a move from the general purpose unit to the vector unit. When the value comes from a load, this can be simplified into a vector load to the right lane. This patch changes the lowering of insert_vector_elt to expose a vector friendly pattern in this situation. This is a step toward fixing <rdar://problem/14170854>. llvm-svn: 186999
* This adds range checking for "ldr Rn, [pc, #imm]" Thumb Mihai Popa2013-07-224-25/+62
| | | | | | | | | | instructions. With this patch: 1. ldr.n is recognized as mnemonic for the short encoding 2. ldr.w is recognized as menmonic for the long encoding 3. ldr will map to either short or long encodings depending on the size of the offset llvm-svn: 186831
* ARM: remove now unneeded custom Asm convertersTim Northover2013-07-224-415/+16
| | | | | | | | After Ulrich's r180677 (thanks!) TableGen is intelligent enough to handle tied constraints involving complex operands properly, so virtually all of the ARM custom converters are now unnecessary. llvm-svn: 186810
* Refactor AnalyzeBranch on ARM. The previous version did not always analyzeLang Hames2013-07-191-88/+67
| | | | | | | | | | | | | | | | | | indirect branches correctly. Under some circumstances, this led to the deletion of basic blocks that were the destination of indirect branches. In that case it left indirect branches to nowhere in the code. This patch replaces, and is more general than either of the previous fixes for indirect-branch-analysis issues, r181161 and r186461. For other branches (not indirect) this refactor should have *almost* identical behavior to the previous version. There are some corner cases where this refactor is able to analyze blocks that the previous version could not (e.g. this necessitated the update to thumb2-ifcvt2.ll). <rdar://problem/14464830> llvm-svn: 186735
* Add a line that got missed off somehow. Sorry about that!Joey Gouly2013-07-191-0/+1
| | | | llvm-svn: 186692
* [ARMv8] Implement the NEON instructions VRINT{N, X, A, Z, M, P}.Joey Gouly2013-07-192-0/+58
| | | | llvm-svn: 186688
* ARM: Add instruction aliases for the Thumb2 PLD/PLDW (literal) alternate form.Tilmann Scheller2013-07-191-1/+6
| | | | | | | | See A8.8.127 in ARM DDI 0406C.b. Related to <rdar://problem/14403733>. llvm-svn: 186682
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