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* [Thumbv8] Fix the value of BLXOperandIndex of isV8EligibleForITWeiming Zhao2014-01-232-4/+3
| | | | | | | | | Originally, BLX was passed as operand #0 in MachineInstr and as operand #2 in MCInst. But now, it's operand #2 in both cases. This patch also removes unnecessary FileCheck in the test case added by r199127. llvm-svn: 199928
* ARM: use litpools for normal i32 imms when compiling minsize.Tim Northover2014-01-233-11/+13
| | | | | | | | | With constant-sharing, litpool loads consume 4 + N*2 bytes of code, but movw/movt pairs consume 8*N. This means litpools are better than movw/movt even with just one use. Other materialisation strategies can still be better though, so the logic is a little odd. llvm-svn: 199891
* Fix inline assembly that switches between ARM and Thumb modesGreg Fitzgerald2014-01-221-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch restores the ARM mode if the user's inline assembly does not. In the object streamer, it ensures that instructions following the inline assembly are encoded correctly and that correct mapping symbols are emitted. For the asm streamer, it emits a .arm or .thumb directive. This patch does not ensure that the inline assembly contains the ADR instruction to switch modes at runtime. The problem we need to solve is code like this: int foo(int a, int b) { int r = a + b; asm volatile( ".align 2 \n" ".arm \n" "add r0,r0,r0 \n" : : "r"(r)); return r+1; } If we compile this function in thumb mode then the inline assembly will switch to arm mode. We need to make sure that we switch back to thumb mode after emitting the inline assembly or we will incorrectly encode the instructions that follow (i.e. the assembly instructions for return r+1). Based on patch by David Peixotto Change-Id: Ib57f6d2d78a22afad5de8693fba6230ff56ba48b llvm-svn: 199818
* ARM IAS: add support for .unwind_raw directiveSaleem Abdulrasool2014-01-213-0/+116
| | | | | | | | | | | | This implements the unwind_raw directive for the ARM IAS. The unwind_raw directive takes the form of a stack offset value followed by one or more bytes representing the opcodes to be emitted. The opcode emitted will interpreted as if it were assembled by the opcode assembler via the standard unwinding directives. Thanks to Logan Chien for an extra test! llvm-svn: 199707
* ARM IAS: support .personalityindexSaleem Abdulrasool2014-01-213-7/+109
| | | | | | | | | | | | | The .personalityindex directive is equivalent to the .personality directive with the ARM EABI personality with the specific index (0, 1, 2). Both of these directives indicate personality routines, so enhance the personality directive handling to take into account personalityindex. Bonus fix: flush the UnwindContext at the beginning of a new function. Thanks to Logan Chien for additional tests! llvm-svn: 199706
* Debug info: On ARM ensure that all __TEXT sections come before theAdrian Prantl2014-01-201-0/+7
| | | | | | | | | optional DWARF sections, so compiling with -g does not result in different code being generated for PC-relative loads. This is reapplying a diet r197922 (__TEXT-only). llvm-svn: 199681
* Revert "Debug info: On ARM ensure that the data sections come before the"Adrian Prantl2014-01-201-13/+0
| | | | | | | | | Cut back on the cargo cult. The order of __DATA sections doesn't affect generated code. This reverts commit r197922. llvm-svn: 199680
* Remove the useless pseudo instructions VDUPfdf and VDUPfqf, replacing them ↵James Molloy2014-01-202-31/+6
| | | | | | with patterns to match VDUPLN. llvm-svn: 199675
* ARM: add tlsldo relocationKai Nacke2014-01-201-0/+3
| | | | | | | | | Add support for the symbol(tlsldo) relocation. This is required in order to solve PR18554. Reviewed by R. Golin, A. Korobeynikov. llvm-svn: 199644
* [ARM] Do not generate Tag_DIV_use=AllowDIVExt when hardware div is ↵Artyom Skrobov2014-01-201-6/+8
| | | | | | non-optional: it should have the default value of AllowDIVIfExists llvm-svn: 199638
* ARM ELF: ensure that the tag types are correctedSaleem Abdulrasool2014-01-191-0/+3
| | | | | | | | Ensure that the tag types are reflected on a replacement. This is particularly important for the compatibility tag which has multiple representations where the last definition wins. llvm-svn: 199577
* ARM: update build attributes for ABI r2.09Saleem Abdulrasool2014-01-191-2/+2
| | | | | | | Update names for the names as per the current ABI errata. Mark deprecated tags as such. llvm-svn: 199576
* Move ARM build attributes into SupportSaleem Abdulrasool2014-01-196-278/+4
| | | | | | | | | | | | This moves the ARM build attributes definitions and support routines into the Support library. The support routines simply permit the conversion of the value to and from a string representation. The movement is prompted in order to permit access to the constants and string representations from readobj in order to facilitate decoding of the attributes section. llvm-svn: 199575
* ARM IAS: remove unnecessary special caseSaleem Abdulrasool2014-01-191-1/+1
| | | | | | | Tag_nodefaults is even and greater than 32 and thus does not need the special check to fall into the correct category. llvm-svn: 199574
* ARM: Let the assembler reject v5 instructions in v4 mode.Benjamin Kramer2014-01-181-1/+2
| | | | | | PR18524. llvm-svn: 199559
* Add MLA alias for ARMv4 support.Renato Golin2014-01-171-9/+14
| | | | | | | | | | Fix MLA defs to use register class GPRnopc. Add encoding tests for multiply instructions. (Alias for MUL/SMLAL/UMLAL added by r199026.) Patch by Zhaoshi. llvm-svn: 199491
* For ARM, fix assertuib failures for some ld/st 3/4 instruction with wirteback.Jiangning Liu2014-01-164-11/+78
| | | | llvm-svn: 199369
* Remove support for armv7f slice. <rdar://problem/12478440>Bob Wilson2014-01-151-1/+0
| | | | | | This was never used for anything so we should just get rid of it. llvm-svn: 199337
* PR 18466: Fix ARM Pseudo ExpansionWeiming Zhao2014-01-151-2/+4
| | | | | | | | | | | | | | | | | | | | When expanding neon pseudo stores, it may miss the implicit uses of sub regs, which may cause post RA scheduler reorder instructions that breakes anti dependency. For example: VST1d64QPseudo %R0<kill>, 16, %Q9_Q10, pred:14, pred:%noreg will be expanded to VST1d64Q %R0<kill>, 16, %D18, pred:14, pred:%noreg; An instruction that defines %D20 may be scheduled before the store by mistake. This patches adds implicit uses for such case. For the example above, it emits: VST1d64Q %R0<kill>, 8, %D18, pred:14, pred:%noreg, %Q9_Q10<imp-use> llvm-svn: 199282
* ARM: correctly determine final tBX_LR in Thumb1 functionsTim Northover2014-01-141-3/+3
| | | | | | | | | | | | | The changes caused by folding an sp-adjustment into a "pop" previously disrupted the forward search for the final real instruction in a terminating block. This switches to a backward search (skipping debug instrs). This fixes PR18399. Patch by Zhaoshi. llvm-svn: 199266
* ARM: add constraint that RdLo != Rn != RdHi for v5 MLA insts.Tim Northover2014-01-141-1/+2
| | | | llvm-svn: 199212
* ARM: remove unused UMAALv5 nodeTim Northover2014-01-141-8/+0
| | | | | | | It was incorrect anyway, since it didn't have accumulator inputs and wasn't even supported on v5. llvm-svn: 199211
* Switch the NEON register class from QPR to DPair.Jakob Stoklund Olesen2014-01-141-1/+1
| | | | | | | | | | | | | The already allocatable DPair superclass contains odd-even D register pair in addition to the even-odd pairs in the QPR register class. There is no reason to constrain the set of D register pairs that can be used for NEON values. Any NEON instructions that require a Q register will automatically constrain the register class to QPR. The allocation order for DPair begins with the QPR registers, so register allocation is unlikely to change much. llvm-svn: 199186
* Make getTargetStreamer return a possibly null pointer.Rafael Espindola2014-01-143-4/+4
| | | | | | | | | This will allow it to be called from target independent parts of the main streamer that don't know if there is a registered target streamer or not. This in turn will allow targets to perform extra actions at specified points in the interface: add extra flags for some labels, extra work during finalization, etc. llvm-svn: 199174
* Fix PR 18369: [Thumbv8] asserts due to inconsistent CPSR liveness of IT blocksWeiming Zhao2014-01-131-0/+3
| | | | | | | | | The issue is caused when Post-RA scheduler reorders a bundle instruction (IT block). However, it only flips the CPSR liveness of the bundle instruction, leaves the instructions inside the bundle unchanged, which causes inconstancy and crashes Thumb2SizeReduction.cpp::ReduceMBB(). llvm-svn: 199127
* ARM: constrain Thumb LDRLIT pseudo-instructions to r0-r7.Tim Northover2014-01-131-4/+5
| | | | | | | | | | | | Previously we only used GPR for the destination placeholder in "ldr rD, [pc, incorrect codegen under the integrated assembler. This should fix both issues (which probably only affect MachO targets at the moment). rdar://problem/15800156 llvm-svn: 199108
* correct target directive handling error handlingSaleem Abdulrasool2014-01-131-24/+44
| | | | | | | | | | | | | | The target specific parser should return `false' if the target AsmParser handles the directive, and `true' if the generic parser should handle the directive. Many of the target specific directive handlers would `return Error' which does not follow these semantics. This change simply changes the target specific routines to conform to the semantis of the ParseDirective correctly. Conformance to the semantics improves diagnostics emitted for the invalid directives. X86 is taken as a sample to ensure that multiple diagnostics are not presented for a single error. llvm-svn: 199068
* ARM IAS: fix diagnostics of improper qualificationSaleem Abdulrasool2014-01-121-0/+1
| | | | | | | | An improper qualifier would result in a superfluous error due to the parser not consuming the remainder of the statement. Simply consume the remainder of the statement to avoid the error. llvm-svn: 199035
* ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructionsSaleem Abdulrasool2014-01-123-65/+89
| | | | | | | | | | | | | The implicit immediate 0 forms are assembly aliases, not distinct instruction encodings. Fix the initial implementation introduced in r198914 to an alias to avoid two separate instruction definitions for the same encoding. An InstAlias is insufficient in this case as the necessary due to the need to add a new additional operand for the implicit zero. By using the AsmPsuedoInst, fall back to the C++ code to transform the instruction to the equivalent _POST_IMM form, inserting the additional implicit immediate 0. llvm-svn: 199032
* Add missing mul aliases for armv4 support. Add checks that armv4 canJoerg Sonnenberger2014-01-121-3/+12
| | | | | | assemble the various mul instructions. llvm-svn: 199026
* ARM IAS: support emitting constant values in target expressionsSaleem Abdulrasool2014-01-111-0/+15
| | | | | | | | A 32-bit immediate value can be formed from a constant expression and loaded into a register. Add support to emit this into an object file. Because this value is a constant, a relocation must *not* be produced for it. llvm-svn: 199023
* Must not produce Tag_CPU_arch_profile for pre-ARMv7 cores (e.g. cortex-m0)Artyom Skrobov2014-01-102-10/+13
| | | | llvm-svn: 198945
* ARM: fix regression caused by r198914Saleem Abdulrasool2014-01-101-8/+17
| | | | | | | | The disassembler would no longer be able to disambiguage between the two variants (explicit immediate #0 vs implicit, omitted #0) for the ldrt, strt, ldrbt, strbt mnemonics as both versions indicated the disassembler routine. llvm-svn: 198944
* ARM IAS: support #:{lower,upper}16: for GNU compatibilitySaleem Abdulrasool2014-01-101-0/+4
| | | | | | | | The GNU assembler supports prefixing the expression with a '#' to indiciate that the value that is being moved is infact a constant. This improves the compatibility of the integrated assembler's parser for this. llvm-svn: 198916
* ARM IAS: support GNU extension for ldrd, strdSaleem Abdulrasool2014-01-102-1/+34
| | | | | | | | | The GNU assembler has an extension that allows for the elision of the paired register (dt2) for the LDRD and STRD mnemonics. Add support for this in the assembly parser. Canonicalise the usage during the instruction parsing from the specified version. llvm-svn: 198915
* ARM IAS: support implicit immediate 0s for {LD,ST}R{B,}TSaleem Abdulrasool2014-01-101-27/+45
| | | | | | | | | | | | | | | | The ARM ARM indicates the mnemonics as follows: ldrbt{<c>}{<q>} <Rt>, [<Rn>], {, #+/-<imm>} ldrt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>} strbt{<c>}{<q>} <Rt>, [<Rn>] {, #<imm>} strt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>} This improves the parser to deal with the implicit immediate 0 for the mnemonics as per the specification. Thanks to Joerg Sonnenberger for the tests! llvm-svn: 198914
* Fix a bug with the ARM thumb2 CBNZ and CBNZ instructions thatKevin Enderby2014-01-101-1/+20
| | | | | | | | | branch to the next instruction. This can not be encoded but can be turned into a NOP. rdar://15062072 llvm-svn: 198904
* Clean up an inconsistency in v7s feature default.Evan Cheng2014-01-091-2/+2
| | | | llvm-svn: 198889
* Put the functionality for printing a value to a raw_ostream as anChandler Carruth2014-01-091-1/+0
| | | | | | | | | | | | operand into the Value interface just like the core print method is. That gives a more conistent organization to the IR printing interfaces -- they are all attached to the IR objects themselves. Also, update all the users. This removes the 'Writer.h' header which contained only a single function declaration. llvm-svn: 198836
* ARM IAS: properly handle expression operandsSaleem Abdulrasool2014-01-082-16/+41
| | | | | | | Operands which involved label arithemetic would previously fail to parse. This corrects that by adding the additional case for the shift operand validation. llvm-svn: 198735
* Move the llvm mangler to lib/IR.Rafael Espindola2014-01-073-3/+3
| | | | | | This makes it available to tools that don't link with target (like llvm-ar). llvm-svn: 198708
* Add ARM fconsts/fconstd aliases for vmov.f32/vmov.f64David Peixotto2014-01-072-7/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds the pre-UAL aliases of fconsts and fconstd for vmov.f32 and vmov.f64. They use an InstAlias rather than a MnemonicAlias to properly support the predicate operand. We need to support encoded 8-bit constants in order to implement the pre-UAL fconsts/fconstd aliases for vmov.f32/vmov.f64, so this commit also fixes parsing of encoded floating point constants used in vmov.f32/vmov.f64 instructions. Now we can support assembly code like this: fconsts s0, #0x70 which is equivalent to vmov.f32 s0, #1.0. Most of the code was already in place to support this feature. Previously the code was trying to accept encoded 8-bit float constants for the vmov.f32/vmov.f64 instructions. It looks like the support for parsing encoded floats was lost in a refactoring in commit r148556 and we did not have any tests in place to catch it. The change in this commit is to keep the parsed value as a 32-bit float instead of a 64-bit double because that is what the isFPImm() function expects to find. There is no loss of precision by using a 32-bit float here because we are still limited to an 8-bit encoded value in the end. Additionally, we explicitly reject encoded 8-bit floats for vmovf.32/64. This is the same as the current behavior, but we now do it explicitly rather than accidently. llvm-svn: 198697
* [arm] Fix an incorrect comment in ARMUnwindOpAsm.h.Logan Chien2014-01-071-1/+1
| | | | llvm-svn: 198696
* Move the LLVM IR asm writer header files into the IR directory, as theyChandler Carruth2014-01-071-1/+1
| | | | | | | | | | | | | | | | | are part of the core IR library in order to support dumping and other basic functionality. Rename the 'Assembly' include directory to 'AsmParser' to match the library name and the only functionality left their -- printing has been in the core IR library for quite some time. Update all of the #includes to match. All of this started because I wanted to have the layering in good shape before I started adding support for printing LLVM IR using the new pass infrastructure, and commandline support for the new pass infrastructure. llvm-svn: 198688
* Re-sort all of the includes with ./utils/sort_includes.py so thatChandler Carruth2014-01-075-9/+7
| | | | | | | | | | subsequent changes are easier to review. About to fix some layering issues, and wanted to separate out the necessary churn. Also comment and sink the include of "Windows.h" in three .inc files to match the usage in Memory.inc. llvm-svn: 198685
* ARM IAS: allow more depth in contextual diagnosticsSaleem Abdulrasool2014-01-071-20/+30
| | | | | | | Switch the context to be SmallVectors. This allows for saving additional context when providing previous emission sites. llvm-svn: 198665
* ARM IAS: refactor unwind contextSaleem Abdulrasool2014-01-071-56/+94
| | | | | | | | Move the unwinding context for the ARM IAS into a helper class. This is purely a structural refactoring. A follow up change allows for recording additional depth to improve diagnostics. llvm-svn: 198664
* ARM Streamer: print out tag namesSaleem Abdulrasool2014-01-071-5/+22
| | | | | | If using verbose asm, print out the friendly name of the tag if possible. llvm-svn: 198663
* ARM IAS: improve .eabi_attribute handlingSaleem Abdulrasool2014-01-076-19/+260
| | | | | | | | Parse tag names as well as expressions. The former is part of the specification, the latter is for improved compatibility with the GNU assembler. Fix attribute value handling to be comformant to the specification. llvm-svn: 198662
* MCParser: introduce Note and use it for ARM AsmParserSaleem Abdulrasool2014-01-071-6/+9
| | | | | | | | Introduce a new virtual method Note into the AsmParser. This completements the existing Warning and Error methods. Use the new method to clean up the output of the unwind routines in the ARM AsmParser. llvm-svn: 198661
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