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* ARM: Add missing two-operand VBIC aliases.Jim Grosbach2012-05-021-0/+2
| | | | llvm-svn: 156019
* Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures.Richard Barton2012-05-021-4/+8
| | | | llvm-svn: 155983
* ARM: Add a few missing add->sub aliases w/ 'w' suffix.Jim Grosbach2012-05-011-0/+11
| | | | | | | | | | | | | | Aliases for adding a negative immediate when using an explicit 'w' suffix. E.g., adds.w r2, #-16 adds.w r2, r2, #-16 addw r2, #-16 addw r2, #-16 addw r2, r2, #-16 rdar://11330769 llvm-svn: 155946
* ARM: allow vanilla expressions for movw/movt.Jim Grosbach2012-05-011-4/+16
| | | | | | | | | | Expressions for movw/movt don't always have an :upper16: or :lower16: on them and that's ok. When they don't, it's just a plain [0-65536] immediate result, effectively the same as a :lower16: variant kind. rdar://10550147 llvm-svn: 155941
* Change the PassManager from a reference to a pointer.Bill Wendling2012-05-011-10/+10
| | | | | | | | | The TargetPassManager's default constructor wants to initialize the PassManager to 'null'. But it's illegal to bind a null reference to a null l-value. Make the ivar a pointer instead. PR12468 llvm-svn: 155902
* ARM: Diagnostics for out of range fixups.Jim Grosbach2012-04-301-34/+52
| | | | | | | | | | | Replace some assert() calls w/ actual diagnostics. In a perfect world, there'd be range checks on these values long before things ever reached this code. For now, though, issuing a better-late-than-never diagnostic is still a big improvement over assert(). rdar://11347287 llvm-svn: 155851
* Fix address calculation error from r155744.Jakob Stoklund Olesen2012-04-301-1/+6
| | | | | | | | | | | | This was exposed by SingleSource/UnitTests/Vector/constpool.c. The computed size of a basic block isn't always a multiple of its known alignment, and that can introduce extra alignment padding after the block. <rdar://problem/11347135> llvm-svn: 155845
* Don't introduce illegal types when creating vmull operations. <rdar://11324364>Bob Wilson2012-04-301-1/+3
| | | | | | | | ARM BUILD_VECTORs created after type legalization cannot use i8 or i16 operands, since those types are not legal. Instead use i32 operands, which will be implicitly truncated by the BUILD_VECTOR to match the element type. llvm-svn: 155824
* Fix a problem with blocks that need to be split twice.Jakob Stoklund Olesen2012-04-281-3/+5
| | | | | | | | | The code could search past the end of the basic block when there was already a constant pool entry after the block. Test case with giant basic block in SingleSource/UnitTests/Vector/constpool.c llvm-svn: 155753
* ARM: Thumb add(sp plus register) asm constraints.Jim Grosbach2012-04-272-2/+22
| | | | | | | | | | Make sure when parsing the Thumb1 sp+register ADD instruction that the source and destination operands match. In thumb2, just use the wide encoding if they don't. In Thumb1, issue a diagnostic. rdar://11219154 llvm-svn: 155748
* ARM: Tweak tADDrSP definition for consistent operand order.Jim Grosbach2012-04-272-3/+3
| | | | | | Make the operand order of the instruction match that of the asm syntax. llvm-svn: 155747
* Track worst case alignment padding more accurately.Jakob Stoklund Olesen2012-04-271-42/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, ARMConstantIslandPass would conservatively compute the address of an aligned basic block as: RoundUpToAlignment(Offset + UnknownPadding) This worked fine for the layout algorithm itself, but it could fool the verify() function because it accounts for alignment padding twice: Once when adding the worst case UnknownPadding, and again by rounding up the fictional block offset. This meant that when optimizeThumb2Instructions would shrink an instruction, the conservative distance estimate could grow. That shouldn't be possible since the woorst case alignment padding wss already included. This patch drops the use of RoundUpToAlignment, and depends only on worst case padding to compute conservative block offsets. This has the weird effect that the computed offset for an aligned block may not be aligned. The important difference is that shrinking an instruction can never cause the estimated distance between two instructions to grow. The estimated distance is always larger than the real distance that only the assembler knows. <rdar://problem/11339352> llvm-svn: 155744
* Fix the order of the operands in the llvm.fma intrinsic patterns for ARM,Lang Hames2012-04-272-24/+25
| | | | | | <rdar://problem/11325085>. llvm-svn: 155724
* Fix ARM assembly parsing for upper case condition codes on IT instructions.Richard Barton2012-04-271-1/+1
| | | | llvm-svn: 155720
* Refactor IT handling not to store the bottom bit of the condition code in ↵Richard Barton2012-04-273-14/+7
| | | | | | the mask operand in the MCInst. llvm-svn: 155700
* Implement a bastardized ABI.Evan Cheng2012-04-272-3/+5
| | | | llvm-svn: 155686
* - thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2Evan Cheng2012-04-272-16/+28
| | | | | | | | instructions. - However, it does support dmb, dsb, isb, mrs, and msr. rdar://11331541 llvm-svn: 155685
* ARM: Thumb ldr(literal) base address alignment is 32-bits.Jim Grosbach2012-04-261-1/+2
| | | | | | | | | | The base address for the PC-relative load is Align(PC,4), so it's the address of the word containing the 16-bit instruction, not the address of the instruction itself. Ugh. rdar://11314619 llvm-svn: 155659
* Use VLD1 in NEON extenting-load patterns instead of VLDR.Tim Northover2012-04-261-56/+59
| | | | | | | On some cores it's a bad idea for performance to mix VFP and NEON instructions and since these patterns are NEON anyway, the NEON load should be used. llvm-svn: 155630
* Test commit.Tim Northover2012-04-261-2/+0
| | | | llvm-svn: 155626
* If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assumeEvan Cheng2012-04-263-7/+16
| | | | | | | | | | the feature set of v7a. This comes about if the user specifies something like -arch armv7 -mcpu=cortex-m3. We shouldn't be generating instructions such as uxtab in this case. rdar://11318438 llvm-svn: 155601
* Unify internal representation of ARM instructions with a register ↵Richard Barton2012-04-252-4/+10
| | | | | | right-shifted by #32. These are stored as shifts by #0 in the MCInst and correctly marshalled when transforming from or to assembly representation. llvm-svn: 155565
* Add ifdef around getSubtargetFeatureName in tablegen output file so that ↵Craig Topper2012-04-251-0/+1
| | | | | | only targets that want the function get it. This prevents other targets from getting an unused function warning. llvm-svn: 155538
* ARM: improved assembler diagnostics for missing CPU features.Jim Grosbach2012-04-242-23/+42
| | | | | | | | | | | When an instruction match is found, but the subtarget features it requires are not available (missing floating point unit, or thumb vs arm mode, for example), issue a diagnostic that identifies what the feature mismatch is. rdar://11257547 llvm-svn: 155499
* ARM: Nuke remnant bogus code.Jim Grosbach2012-04-241-2/+0
| | | | | | | | r154362 was supposed to delete this bit, but obviously didn't. rdar://11305594 llvm-svn: 155465
* Refactor Thumb ITState handling in ARM Disassembler to more efficiently use ↵Richard Barton2012-04-241-31/+69
| | | | | | its vector llvm-svn: 155439
* Tidy up. 80 columns, whitespace, et. al.Jim Grosbach2012-04-234-59/+65
| | | | llvm-svn: 155399
* This patch fixes a problem which arose when using the Post-RA schedulerPreston Gurd2012-04-232-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on X86 Atom. Some of our tests failed because the tail merging part of the BranchFolding pass was creating new basic blocks which did not contain live-in information. When the anti-dependency code in the Post-RA scheduler ran, it would sometimes rename the register containing the function return value because the fact that the return value was live-in to the subsequent block had been lost. To fix this, it is necessary to run the RegisterScavenging code in the BranchFolding pass. This patch makes sure that the register scavenging code is invoked in the X86 subtarget only when post-RA scheduling is being done. Post RA scheduling in the X86 subtarget is only done for Atom. This patch adds a new function to the TargetRegisterClass to control whether or not live-ins should be preserved during branch folding. This is necessary in order for the anti-dependency optimizations done during the PostRASchedulerList pass to work properly when doing Post-RA scheduling for the X86 in general and for the Intel Atom in particular. The patch adds and invokes the new function trackLivenessAfterRegAlloc() instead of using the existing requiresRegisterScavenging(). It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of requiresRegisterScavenging(). It changes the all the targets that implemented requiresRegisterScavenging() to also implement trackLivenessAfterRegAlloc(). It adds an assertion in the Post RA scheduler to make sure that post RA liveness information is available when it is needed. It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order to avoid running into the added assertion. Finally, this patch restores the use of anti-dependency checking (which was turned off temporarily for the 3.1 release) for Intel Atom in the Post RA scheduler. Patch by Andy Zhang! Thanks to Jakob and Anton for their reviews. llvm-svn: 155395
* ARM: VSLI two-operand assmebly aliases are tblgen'erated.Jim Grosbach2012-04-231-19/+0
| | | | llvm-svn: 155393
* ARM: tblgen'erate VSRA/VRSRA/VSRI assembly two-operand aliases.Jim Grosbach2012-04-231-58/+4
| | | | llvm-svn: 155392
* ARM: vqdmulh two-operand aliases are tblgen'erated now.Jim Grosbach2012-04-231-11/+0
| | | | llvm-svn: 155387
* ARM: Initialize the HasRAS bit.Benjamin Kramer2012-04-221-0/+1
| | | | | | Found by valgrind. llvm-svn: 155313
* ARM: tblgen'erate more NEON two-operand aliases.Jim Grosbach2012-04-201-39/+12
| | | | | | VMUL and VEXT. llvm-svn: 155258
* ARM: tblgen'erate more NEON two-operand aliases.Jim Grosbach2012-04-201-153/+4
| | | | llvm-svn: 155254
* ARM: Update NEON assembly two-operand aliases.Jim Grosbach2012-04-202-305/+14
| | | | | | | | Use the new TwoOperandAliasConstraint to handle lots of the two-operand aliases for NEON instructions. There's still more to go, but this is a good chunk of them. llvm-svn: 155210
* Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-209-110/+118
| | | | | | since they are equivalent. llvm-svn: 155188
* ARM some VFP tblgen'erated two-operand aliases.Jim Grosbach2012-04-201-16/+8
| | | | llvm-svn: 155178
* ARM let TableGen handle a few two-operand aliases.Jim Grosbach2012-04-191-121/+9
| | | | | | No need for these explicit aliases anymore. Nuke 'em. llvm-svn: 155173
* Added support for disassembling unpredictable swp/swpb ARM instructions.Silviu Baranga2012-04-183-2/+7
| | | | llvm-svn: 155004
* Fix the bahavior of the disassembler when decoding unpredictable mrs ↵Silviu Baranga2012-04-181-5/+15
| | | | | | instructions on ARM. Now the diasassembler emmits warnings instead of errors. llvm-svn: 155002
* Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the ↵Silviu Baranga2012-04-182-4/+36
| | | | | | disassembler. Since the upredicability conditions are complex, C++ code was added to handle them. llvm-svn: 155001
* Fixed decoding for the ARM cdp2 instruction. The restriction on the ↵Silviu Baranga2012-04-181-1/+6
| | | | | | coprocessor number was removed for this instruction. llvm-svn: 155000
* Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM ↵Silviu Baranga2012-04-181-2/+10
| | | | | | instructions in the disassembler. llvm-svn: 154999
* Typo.Chad Rosier2012-04-171-1/+1
| | | | llvm-svn: 154953
* Remove unused CCIfSubtarget.Jay Foad2012-04-171-4/+0
| | | | llvm-svn: 154921
* Fix bad EXTRACT_SUBREG in instruction selection for extending-loads on NEON.James Molloy2012-04-171-8/+44
| | | | llvm-svn: 154915
* Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)Kevin Enderby2012-04-171-7/+1
| | | | | | | instructions with writebacks. And add test a case for all opcodes handed by DecodeVLD2DupInstruction() in ARMDisassembler.cpp . llvm-svn: 154884
* ARM two-operand forms for vhadd and vhsub instructions.Jim Grosbach2012-04-161-0/+62
| | | | | | rdar://11252521 llvm-svn: 154875
* ARM handle :lower16: and :upper16: after a '#' prefix.Jim Grosbach2012-04-161-13/+17
| | | | | | rdar://11252521 llvm-svn: 154862
* ARM assembly two-operand forms for VRSHL.Jim Grosbach2012-04-161-1/+36
| | | | | | rdar://11252521 llvm-svn: 154840
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