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* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-2219-21/+38
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
* [cleanup] Lift using directives, DEBUG_TYPE definitions, and even someChandler Carruth2014-04-222-5/+5
| | | | | | | | | | | | system headers above the includes of generated '.inc' files that actually contain code. In a few targets this was already done pretty consistently, but it wasn't done *really* consistently anywhere. It is strictly cleaner IMO and necessary in a bunch of places where the DEBUG_TYPE is referenced from the generated code. Consistency with the necessary places trumps. Hopefully the build bots are OK with the movement of intrin.h... llvm-svn: 206838
* [Modules] Make Support/Debug.h modular. This requires it to not changeChandler Carruth2014-04-212-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | behavior based on other files defining DEBUG_TYPE, which means it cannot define DEBUG_TYPE at all. This is actually better IMO as it forces folks to define relevant DEBUG_TYPEs for their files. However, it requires all files that currently use DEBUG(...) to define a DEBUG_TYPE if they don't already. I've updated all such files in LLVM and will do the same for other upstream projects. This still leaves one important change in how LLVM uses the DEBUG_TYPE macro going forward: we need to only define the macro *after* header files have been #include-ed. Previously, this wasn't possible because Debug.h required the macro to be pre-defined. This commit removes that. By defining DEBUG_TYPE after the includes two things are fixed: - Header files that need to provide a DEBUG_TYPE for some inline code can do so by defining the macro before their inline code and undef-ing it afterward so the macro does not escape. - We no longer have rampant ODR violations due to including headers with different DEBUG_TYPE definitions. This may be mostly an academic violation today, but with modules these types of violations are easy to check for and potentially very relevant. Where necessary to suppor headers with DEBUG_TYPE, I have moved the definitions below the includes in this commit. I plan to move the rest of the DEBUG_TYPE macros in LLVM in subsequent commits; this one is big enough. The comments in Debug.h, which were hilariously out of date already, have been updated to reflect the recommended practice going forward. llvm-svn: 206822
* [C++11] Replace OwningPtr with std::unique_ptr in places where it doesn't ↵Benjamin Kramer2014-04-212-5/+3
| | | | | | | | break the API. No functionality change. llvm-svn: 206740
* Remove some empty statementsAlp Toker2014-04-192-2/+2
| | | | | | Cleanup only. llvm-svn: 206710
* Change the ARM assembler to require a :lower16: or :upper16 on non-constantKevin Enderby2014-04-182-5/+29
| | | | | | | | | | | | | | | | | | | | | | expressions for mov instructions instead of silently truncating by default. For the ARM assembler, we want to avoid misleadingly allowing something like "mov r0, <symbol>" especially when we turn it into a movw and the expression <symbol> does not have a :lower16: or :upper16" as part of the expression. We don't want the behavior of silently truncating, which can be unexpected and lead to bugs that are difficult to find since this is an easy mistake to make. This does change the previous behavior of llvm but actually matches an older gnu assembler that would not allow this but print less useful errors of like “invalid constant (0x927c0) after fixup” and “unsupported relocation on symbol foo”. The error for llvm is "immediate expression for mov requires :lower16: or :upper16" with correct location information on the operand as shown in the added test cases. rdar://12342160 llvm-svn: 206669
* Atomics: promote ARM's IR-based atomics pass to CodeGen.Tim Northover2014-04-176-410/+89
| | | | | | | | | | | | Still only 32-bit ARM using it at this stage, but the promotion allows direct testing via opt and is a reasonably self-contained patch on the way to switching ARM64. At this point, other targets should be able to make use of it without too much difficulty if they want. (See ARM64 commit coming soon for an example). llvm-svn: 206485
* Convert SelectionDAG::getVTList to use ArrayRefCraig Topper2014-04-161-2/+2
| | | | llvm-svn: 206357
* FastISel: constrain the RegClass of operands when emitting instructions.Tim Northover2014-04-151-19/+0
| | | | | | | | | | | ARM64 suffered multiple -verify-machineinstr failures (principally over the xsp/xzr issue) because FastISel was completely ignoring which subset of the general-purpose registers each instruction required. More fixes are coming in ARM64 specific FastISel, but this should cover the generic problems. llvm-svn: 206283
* [MC] Require an MCContext when constructing an MCDisassembler.Lang Hames2014-04-151-8/+12
| | | | | | | | | | | | | | | | This patch re-introduces the MCContext member that was removed from MCDisassembler in r206063, and requires that an MCContext be passed in at MCDisassembler construction time. (Previously the MCContext member had been initialized in an ad-hoc fashion after construction). The MCCContext member can be used by MCDisassembler sub-classes to construct constant or target-specific MCExprs. This patch updates disassemblers for in-tree targets, and provides the MCRegisterInfo instance that some disassemblers were using through the MCContext (previously those backends were constructing their own MCRegisterInfo instances). llvm-svn: 206241
* Spell the specialization namespace correctly.Benjamin Kramer2014-04-122-2/+6
| | | | | | Not sure why clang didn't diagnose this (GCC does). llvm-svn: 206117
* Make helper static and place random global into the llvm namespace.Benjamin Kramer2014-04-123-4/+4
| | | | llvm-svn: 206116
* For the ARM integrated assembler add checking of theKevin Enderby2014-04-103-433/+894
| | | | | | | | | | | | | | | | | | | alignments on vld/vst instructions. And report errors for alignments that are not supported. While this is a large diff and an big test case, the changes are very straight forward. But pretty much had to touch all vld/vst instructions changing the addrmode to one of the new ones that where added will do the proper checking for the specific instruction. FYI, re-committing this with a tweak so MemoryOp's default constructor is trivial and will work with MSVC 2012. Thanks to Reid Kleckner and Jim Grosbach for help with the tweak. rdar://11312406 llvm-svn: 205986
* Revert "For the ARM integrated assembler add checking of the alignments on ↵Reid Kleckner2014-04-103-894/+432
| | | | | | | | | | | | | vld/vst instructions. And report errors for alignments that are not supported." It doesn't build with MSVC 2012, because MSVC doesn't allow union members that have non-trivial default constructors. This change added 'SMLoc AlignmentLoc' to MemoryOp, which made MemoryOp's default ctor non-trivial. This reverts commit r205930. llvm-svn: 205944
* For the ARM integrated assembler add checking of theKevin Enderby2014-04-093-432/+894
| | | | | | | | | | | | | | | alignments on vld/vst instructions. And report errors for alignments that are not supported. While this is a large diff and an big test case, the changes are very straight forward. But pretty much had to touch all vld/vst instructions changing the addrmode to one of the new ones that where added will do the proper checking for the specific instruction. rdar://11312406 llvm-svn: 205930
* Fix some doc and comment typosAlp Toker2014-04-091-1/+1
| | | | llvm-svn: 205899
* ARM MC: 80 columnSaleem Abdulrasool2014-04-091-3/+5
| | | | llvm-svn: 205833
* ARM MC: sort source files in CMakeListsSaleem Abdulrasool2014-04-091-3/+3
| | | | llvm-svn: 205832
* Fix the ARM VLD3 (single 3-element structure to all lanes)Kevin Enderby2014-04-081-1/+1
| | | | | | | | | | | | | | | size 16 double-spaced registers instruction printing. This: vld3.16 {d0[], d2[], d4[]}, [r4]! was being printed as: vld3.16 {d0[], d1[], d2[]}, [r4]! rdar://16531387 llvm-svn: 205779
* ARM: consolidate MachO checks for ARM asm parserSaleem Abdulrasool2014-04-051-84/+28
| | | | | | | | | | | | | | | | | | | This consolidates the duplicated MachO checks in the directive parsing for various directives that are unsupported for Mach-O. The error message change is unimportant as this restores the behaviour to that prior to the addition of the new directive handling. Furthermore, use a more direct check for MachO targeting rather than an indirect feature check of the assembler. Also simplify the test execution command to avoid temporary files. Further more, perform the check in both object and assembly emission. Whether all non-applicable directives are handled is another question. .fnstart is marked as being unsupported, however, the complementary .fnend is not. The additional unwinding directives are also still honoured. This change does not change that, though, it would be good to validate and mark them as being unsupported if they are unsupported for the MachO emission. llvm-svn: 205678
* Fix for PR18921 (LDRD/STRD part)::Stepan Dyatkovskiy2014-04-042-25/+14
| | | | | | | | Removed "GNU Assembler extension (compatibility)" definitions from ARMInstrInfo.td Fixed ARMAsmParser::ParseInstruction GNU compatability branch, so it also works for thumb mode from now. Added new tests. llvm-svn: 205622
* Fixed register class in STRD instruction for Thumb2 mode.Stepan Dyatkovskiy2014-04-041-1/+1
| | | | llvm-svn: 205612
* Make consistent use of MCPhysReg instead of uint16_t throughout the tree.Craig Topper2014-04-046-17/+17
| | | | llvm-svn: 205610
* ARM: Range based for-loop over block predecessors.Jim Grosbach2014-04-041-3/+2
| | | | | | No functional change. llvm-svn: 205604
* ARM: Use range-based for loops in frame lowering.Jim Grosbach2014-04-041-25/+19
| | | | | | No functional change. llvm-svn: 205602
* Tidy up. 80 columns.Jim Grosbach2014-04-032-3/+3
| | | | llvm-svn: 205584
* Tidy up. Trailing whitespace.Jim Grosbach2014-04-0311-41/+41
| | | | llvm-svn: 205583
* ARM: tell LLVM about zext properties of ldrexb/ldrexhTim Northover2014-04-032-8/+14
| | | | | | | | | | | | | Implementing this via ComputeMaskedBits has two advantages: + It actually works. DAGISel doesn't deal with the chains properly in the previous pattern-based solution, so they never trigger. + The information can be used in other DAG combines, as well as the trivial "get rid of truncs". For example if the trunc is in a different basic block. rdar://problem/16227836 llvm-svn: 205540
* ARM: skip cmpxchg failure barrier if ordering is monotonic.Tim Northover2014-04-031-12/+21
| | | | | | | | | | The terminal barrier of a cmpxchg expansion will be either Acquire or SequentiallyConsistent. In either case it can be skipped if the operation has Monotonic requirements on failure. rdar://problem/15996804 llvm-svn: 205535
* ARM: expand atomic ldrex/strex loops in IRTim Northover2014-04-038-1086/+408
| | | | | | | | | | | | | | | | | | | | | | | | | The previous situation where ATOMIC_LOAD_WHATEVER nodes were expanded at MachineInstr emission time had grown to be extremely large and involved, to account for the subtly different code needed for the various flavours (8/16/32/64 bit, cmpxchg/add/minmax). Moving this transformation into the IR clears up the code substantially, and makes future optimisations much easier: 1. an atomicrmw followed by using the *new* value can be more efficient. As an IR pass, simple CSE could handle this efficiently. 2. Making use of cmpxchg success/failure orderings only has to be done in one (simpler) place. 3. The common "cmpxchg; did we store?" idiom can be exposed to optimisation. I intend to gradually improve this situation within the ARM backend and make sure there are no hidden issues before moving the code out into CodeGen to be shared with (at least ARM64/AArch64, though I think PPC & Mips could benefit too). llvm-svn: 205525
* PR19320:Stepan Dyatkovskiy2014-04-031-4/+9
| | | | | | | The trouble as in ARMAsmParser, in ParseInstruction method. It assumes that ARM::R12 + 1 == ARM::SP. It is wrong, since ARM::<Register> codes are generated by tablegen and actually could be any random numbers. llvm-svn: 205524
* [ARM] When generating a vpaddl node the input lane type is not always the ↵Silviu Baranga2014-04-031-2/+5
| | | | | | | | | | type of the add operation since extract_vector_elt can perform an extend operation. Get the input lane type from the vector on which we're performing the vpaddl operation on and extend or truncate it to the output type of the original add node. llvm-svn: 205523
* ARM: Use __STACK_LIMIT symbol for segmented stacksOliver Stannard2014-04-031-1/+1
| | | | | | | We cannot use STACK_LIMIT, as it is not reserved for the compiler by the C spec. llvm-svn: 205516
* ARM: update subtarget information for Windows on ARMSaleem Abdulrasool2014-04-026-12/+83
| | | | | | | Update the subtarget information for Windows on ARM. This enables using the MC layer to target Windows on ARM. llvm-svn: 205459
* Simplify resolveFrameIndex() signature.Jim Grosbach2014-04-024-12/+8
| | | | | | | | Just pass a MachineInstr reference rather than an MBB iterator. Creating a MachineInstr& is the first thing every implementation did anyway. llvm-svn: 205453
* ARM: cortex-m0 doesn't support unaligned memory access.Jim Grosbach2014-04-021-1/+6
| | | | | | | | | | | | Unlike other v6+ processors, cortex-m0 never supports unaligned accesses. From the v6m ARM ARM: "A3.2 Alignment support: ARMv6-M always generates a fault when an unaligned access occurs." rdar://16491560 llvm-svn: 205452
* ARM: Add support for segmented stacksOliver Stannard2014-04-025-0/+378
| | | | | | Patch by Alex Crichton, ILyoan, Luqman Aden and Svetoslav. llvm-svn: 205430
* Remove duplicated DMB instructionsRenato Golin2014-04-024-0/+104
| | | | | | | | | ARM specific optimiztion, finding places in ARM machine code where 2 dmbs follow one another, and eliminating one of them. Patch by Reinoud Elhorst. llvm-svn: 205409
* ARM: rename ARMle/ARMbe with ARMLE/ARMBE, and Thumble/Thumbbe with ↵Christian Pirker2014-04-0110-114/+114
| | | | | | ThumbLE/ThumbBE llvm-svn: 205317
* ARM: teach LLVM that Cortex-A7 is very similar to A8.Tim Northover2014-04-013-9/+11
| | | | llvm-svn: 205314
* ARM: add cyclone CPU with ZeroCycleZeroing feature.Tim Northover2014-04-015-6/+45
| | | | | | | | The Cyclone CPU is similar to swift for most LLVM purposes, but does have two preferred instructions for zeroing a VFP register. This teaches LLVM about them. llvm-svn: 205309
* ARM: fix typoSaleem Abdulrasool2014-03-311-1/+1
| | | | llvm-svn: 205233
* ARM: change parameter names of the ELFARMAsmBackend constructorChristian Pirker2014-03-311-2/+2
| | | | | | | I removed the underscore at the beginning of the parameter name, because of a comment from Tim. llvm-svn: 205215
* Recommitted fix for PR18931, with extended tests set.Stepan Dyatkovskiy2014-03-292-2/+20
| | | | | | | | | | | | | Issue subject: Crash using integrated assembler with immediate arithmetic Fix description: Expressions like 'cmp r0, #(l1 - l2) >> 3' could not be evaluated on asm parsing stage, since it is impossible to resolve labels on this stage. In the end of stage we still have expression (MCExpr). Then, when we want to encode it, we expect it to be an immediate, but it still an expression. Patch introduces a Fixup (MCFixup instance), that is processed after main encoding stage. llvm-svn: 205094
* Completely rewrite ELFObjectWriter::RecordRelocation.Rafael Espindola2014-03-295-178/+31
| | | | | | | | | | | | | | | | | | | I started trying to fix a small issue, but this code has seen a small fix too many. The old code was fairly convoluted. Some of the issues it had: * It failed to check if a symbol difference was in the some section when converting a relocation to pcrel. * It failed to check if the relocation was already pcrel. * The pcrel value computation was wrong in some cases (relocation-pc.s) * It was missing quiet a few cases where it should not convert symbol relocations to section relocations, leaving the backends to patch it up. * It would not propagate the fact that it had changed a relocation to pcrel, requiring a quiet nasty work around in ARM. * It was missing comments. llvm-svn: 205076
* Add const.Rafael Espindola2014-03-281-2/+2
| | | | llvm-svn: 205013
* Add ARM big endian Target (armeb, thumbeb)Christian Pirker2014-03-2815-85/+410
| | | | | | Reviewed at http://llvm-reviews.chandlerc.com/D3095 llvm-svn: 205007
* Remove another unused argument.Rafael Espindola2014-03-271-3/+2
| | | | llvm-svn: 204961
* Remove unused argument.Rafael Espindola2014-03-271-4/+2
| | | | llvm-svn: 204956
* Rejected r204899 and r204900 due to remaining test failures on ↵Stepan Dyatkovskiy2014-03-271-17/+1
| | | | | | cmake-llvm-x86_64-linux buildbot. llvm-svn: 204901
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