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* Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported.Lang Hames2011-11-081-0/+7
| | | | | | | | Add support for trimming constants to GetDemandedBits. This fixes some funky constant generation that occurs when stores are expanded for targets that don't support unaligned stores natively. llvm-svn: 144102
* Added invariant field to the DAG.getLoad method and changed all calls.Pete Cooper2011-11-082-33/+39
| | | | | | When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses llvm-svn: 144100
* Make sure to mark vector extload's as expand on ARM. Fixes PR11319.Eli Friedman2011-11-081-9/+11
| | | | llvm-svn: 144057
* Enable support for returning i1, i8, and i16. Nothing special todo as it's theChad Rosier2011-11-082-1/+9
| | | | | | | | callee's responsibility to sign or zero-extend the return value. The additional test case just checks to make sure the calls are selected (i.e., -fast-isel-abort doesn't assert). llvm-svn: 144047
* Allow i1 to be promoted to i32 for ARM AAPCS and AAPCS-VFP calling ↵Chad Rosier2011-11-071-1/+1
| | | | | | convention as well. llvm-svn: 144021
* Simplify some uses of utohexstr.Benjamin Kramer2011-11-071-2/+2
| | | | | | As a side effect hex is printed lowercase instead of uppercase now. llvm-svn: 144013
* Replace (Lower|Upper)caseString in favor of StringRef's newest methods.Benjamin Kramer2011-11-063-17/+10
| | | | llvm-svn: 143891
* Add support for passing i1, i8, and i16 call parameters. Also, be sure toChad Rosier2011-11-051-28/+16
| | | | | | | zero-extend the constant integer encoding. Test case provides testing for both call parameters and materialization of i1, i8, and i16 types. llvm-svn: 143821
* Allow i1 to be promoted to i32 for ARM APCS calling convention.Chad Rosier2011-11-051-1/+1
| | | | llvm-svn: 143755
* Cannot create a result register for non-legal types.Chad Rosier2011-11-041-1/+2
| | | | llvm-svn: 143749
* When materializing an i32, SExt vs ZExt doesn't matter when we're trying to fitChad Rosier2011-11-041-1/+1
| | | | | | | | in a 16-bit immediate. However, for the shorter non-legal types (i.e., i1, i8, i16) we should not sign-extend. This prevents us from materializing things such as 'true' (i.e., i1 1). llvm-svn: 143743
* Enable support for materializing i1, i8, and i16 integers via move immediate.Chad Rosier2011-11-041-6/+11
| | | | llvm-svn: 143739
* build/cmake: Use tblgen macro directly instead of llvm_tablegen, which justDaniel Dunbar2011-11-041-13/+13
| | | | | | added a layer of indirection with no value (not even conciseness). llvm-svn: 143727
* Fix some minor scheduling itinerary bug. It's not expected to actually ↵Evan Cheng2011-11-041-14/+20
| | | | | | affect codegen. llvm-svn: 143675
* Indentation.Chad Rosier2011-11-041-1/+1
| | | | llvm-svn: 143670
* Add fast-isel support for returning i1, i8, and i16.Chad Rosier2011-11-041-6/+19
| | | | llvm-svn: 143669
* Reapply r143206, with fixes. Disallow physical register lifetimesDan Gohman2011-11-031-3/+16
| | | | | | | across calls, and only check for nested dependences on the special call-sequence-resource register. llvm-svn: 143660
* build: Add initial cut at LLVMBuild.txt files.Daniel Dunbar2011-11-036-0/+150
| | | | llvm-svn: 143634
* Add support for sign-extending non-legal types in SelectSIToFP().Chad Rosier2011-11-031-5/+14
| | | | llvm-svn: 143603
* Fixed parameter name.Lang Hames2011-11-022-3/+3
| | | | llvm-svn: 143594
* Try to lower memset/memcpy/memmove to vector instructions on ARM where the ↵Lang Hames2011-11-022-1/+34
| | | | | | alignment permits. llvm-svn: 143582
* Add support for comparing integer non-legal types.Chad Rosier2011-11-021-16/+33
| | | | llvm-svn: 143559
* Fix the issue that r143552 was trying to address the _right_ way. ↵Owen Anderson2011-11-021-2/+6
| | | | | | One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction. llvm-svn: 143557
* The rules disallowing single-register reglist operands only apply to the POP ↵Owen Anderson2011-11-021-5/+1
| | | | | | alias, not to LDM/STM instructions. Revert r143552. llvm-svn: 143553
* Register list operands are not allowed to contain only a single register. ↵Owen Anderson2011-11-021-1/+5
| | | | | | Alternate encodings are used in that case. llvm-svn: 143552
* Factor out an EmitIntExt function. No functionality change intended.Chad Rosier2011-11-021-31/+37
| | | | llvm-svn: 143547
* Factor out a SelectTrunc function. No functionality change intended.Chad Rosier2011-11-021-17/+28
| | | | llvm-svn: 143523
* ARM label operands can be quoted.Jim Grosbach2011-11-011-0/+1
| | | | | | For example, labels from Objective-C sources. llvm-svn: 143511
* ARM label operands can have an optional '#' before them.Jim Grosbach2011-11-011-6/+4
| | | | llvm-svn: 143510
* Fix disassembly of some VST1 instructions.Owen Anderson2011-11-011-5/+19
| | | | llvm-svn: 143507
* ARM VLD/VST assembly parsing for symbolic address operands.Jim Grosbach2011-11-013-2/+36
| | | | llvm-svn: 143413
* ARM VST1 w/ writeback assembly parsing and encoding.Jim Grosbach2011-10-315-59/+168
| | | | llvm-svn: 143369
* ARM writeback vs. stride operands for VST/VLD.Jim Grosbach2011-10-311-239/+240
| | | | | | | The _fixed variants have a writeback operand, but not a stride operand. Split the conditional flag to distinguish the cases. llvm-svn: 143356
* More not-crashing NEON disassembly updates for the vld refactoring.Owen Anderson2011-10-311-0/+4
| | | | llvm-svn: 143351
* Revert r143206, as there are still some failing tests.Dan Gohman2011-10-291-16/+3
| | | | llvm-svn: 143262
* ARM mode 'mov' to 'mvn' assembler alias.Jim Grosbach2011-10-282-2/+30
| | | | llvm-svn: 143237
* Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm".Jim Grosbach2011-10-282-1/+29
| | | | | | | | | | | When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example, mov r2, #-3 becomes mvn r2, #2 rdar://10349224 llvm-svn: 143235
* Specify that the high bit of the alignment field is fixed to 0 on these ↵Owen Anderson2011-10-281-2/+2
| | | | | | instructions. llvm-svn: 143220
* Reapply r143202, with a manual decoding hook for SWP. This change ↵Owen Anderson2011-10-283-1/+27
| | | | | | inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle. llvm-svn: 143208
* Reapply r143177 and r143179 (reverting r143188), with schedulerDan Gohman2011-10-281-3/+16
| | | | | | | | | fixes: Use a separate register, instead of SP, as the calling-convention resource, to avoid spurious conflicts with actual uses of SP. Also, fix unscheduling of calling sequences, which can be triggered by pseudo-two-address dependencies. llvm-svn: 143206
* Revert r143202.Owen Anderson2011-10-281-1/+1
| | | | llvm-svn: 143203
* Specify fixed bits on CPS instructions to enable roundtripping.Owen Anderson2011-10-281-1/+1
| | | | llvm-svn: 143202
* Thumb2 ADD/SUB instructions encoding selection outside IT block.Jim Grosbach2011-10-281-0/+21
| | | | | | | | | | | Outside an IT block, "add r3, #2" should select a 32-bit wide encoding rather than generating an error indicating the 16-bit encoding is only legal in an IT block (outside, the 'S' suffic is required for the 16-bit encoding). rdar://10348481 llvm-svn: 143201
* Speculatively disable Dan's commits 143177 and 143179 to see ifDuncan Sands2011-10-281-16/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | it fixes the dragonegg self-host (it looks like gcc is miscompiled). Original commit messages: Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW on every node as it legalizes them. This makes it easier to use hasOneUse() heuristics, since unneeded nodes can be removed from the DAG earlier. Make LegalizeOps visit the DAG in an operands-last order. It previously used operands-first, because LegalizeTypes has to go operands-first, and LegalizeTypes used to be part of LegalizeOps, but they're now split. The operands-last order is more natural for several legalization tasks. For example, it allows lowering code for nodes with floating-point or vector constants to see those constants directly instead of seeing the lowered form (often constant-pool loads). This makes some things somewhat more complicated today, though it ought to allow things to be simpler in the future. It also fixes some bugs exposed by Legalizing using RAUW aggressively. Remove the part of LegalizeOps that attempted to patch up invalid chain operands on libcalls generated by LegalizeTypes, since it doesn't work with the new LegalizeOps traversal order. Instead, define what LegalizeTypes is doing to be correct, and transfer the responsibility of keeping calls from having overlapping calling sequences into the scheduler. Teach the scheduler to model callseq_begin/end pairs as having a physical register definition/use to prevent calls from having overlapping calling sequences. This is also somewhat complicated, though there are ways it might be simplified in the future. This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others. Please direct high-level questions about this patch to management. Delete #if 0 code accidentally left in. llvm-svn: 143188
* Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUWDan Gohman2011-10-281-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on every node as it legalizes them. This makes it easier to use hasOneUse() heuristics, since unneeded nodes can be removed from the DAG earlier. Make LegalizeOps visit the DAG in an operands-last order. It previously used operands-first, because LegalizeTypes has to go operands-first, and LegalizeTypes used to be part of LegalizeOps, but they're now split. The operands-last order is more natural for several legalization tasks. For example, it allows lowering code for nodes with floating-point or vector constants to see those constants directly instead of seeing the lowered form (often constant-pool loads). This makes some things somewhat more complicated today, though it ought to allow things to be simpler in the future. It also fixes some bugs exposed by Legalizing using RAUW aggressively. Remove the part of LegalizeOps that attempted to patch up invalid chain operands on libcalls generated by LegalizeTypes, since it doesn't work with the new LegalizeOps traversal order. Instead, define what LegalizeTypes is doing to be correct, and transfer the responsibility of keeping calls from having overlapping calling sequences into the scheduler. Teach the scheduler to model callseq_begin/end pairs as having a physical register definition/use to prevent calls from having overlapping calling sequences. This is also somewhat complicated, though there are ways it might be simplified in the future. This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others. Please direct high-level questions about this patch to management. llvm-svn: 143177
* ARM Allow 'q' registers in VLD/VST vector lists.Jim Grosbach2011-10-281-4/+47
| | | | | | | | Just treat it as if the constituent D registers where specified. rdar://10348896 llvm-svn: 143167
* Add some NEON stores to the VLD decoding hook that were accidentally omitted ↵Owen Anderson2011-10-271-0/+4
| | | | | | previously. llvm-svn: 143162
* Also set addrmode6 alignment when align==size.Jakob Stoklund Olesen2011-10-271-1/+1
| | | | | | | Previously, we were only setting the alignment bits on over-aligned loads and stores. llvm-svn: 143160
* ARM isel for vld1, opcode selection for register stride post-index pseudos.Jim Grosbach2011-10-271-0/+4
| | | | llvm-svn: 143158
* Avoid partial CPSR dependency from loop backedges. rdar://10357570Evan Cheng2011-10-271-24/+43
| | | | llvm-svn: 143145
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