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* Add a missing def flag.Jakob Stoklund Olesen2012-08-211-4/+2
| | | | | | | | | | *** Bad machine code: Explicit definition marked as use *** - function: test_cos - basic block: BB#0 L.entry (0x7ff2a2024fd0) - instruction: VSETLNi32 %D11, %D11<undef>, %R0, 0, pred:14, pred:%noreg, %Q5<imp-use,kill>, %Q5<imp-def> - operand 0: %D11 llvm-svn: 162247
* Use a SmallPtrSet to dedup successors in EmitSjLjDispatchBlock.Jakob Stoklund Olesen2012-08-201-3/+2
| | | | | | | The test case ARM/2011-05-04-MultipleLandingPadSuccs.ll was creating duplicate successor list entries. llvm-svn: 162222
* Remove the CAND/COR/CXOR custom ISD nodes and their select code.Jakob Stoklund Olesen2012-08-183-174/+0
| | | | | | | These nodes are no longer needed because the peephole pass can fold CMOV+AND into ANDCC etc. llvm-svn: 162179
* Remove virtual from many methods. These methods replace methods in the base ↵Craig Topper2012-08-181-38/+40
| | | | | | class, but the base class methods aren't virtual so it just increased call overhead. llvm-svn: 162178
* Also combine zext/sext into selects for ARM.Jakob Stoklund Olesen2012-08-181-47/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This turns common i1 patterns into predicated instructions: (add (zext cc), x) -> (select cc (add x, 1), x) (add (sext cc), x) -> (select cc (add x, -1), x) For a function like: unsigned f(unsigned s, int x) { return s + (x>0); } We now produce: cmp r1, #0 it gt addgt.w r0, r0, #1 Instead of: movs r2, #0 cmp r1, #0 it gt movgt r2, #1 add r0, r2 llvm-svn: 162177
* Also pass logical ops to combineSelectAndUse.Jakob Stoklund Olesen2012-08-181-9/+42
| | | | | | | | | | | | | | | | Add these transformations to the existing add/sub ones: (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) (or (select cc, 0, c), x) -> (select cc, x, (or, x, c)) (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c)) The selects can then be transformed to a single predicated instruction by peephole. This transformation will make it possible to eliminate the ISD::CAND, COR, and CXOR custom DAG nodes. llvm-svn: 162176
* fp16-to-fp32 conversion instructions are available in Thumb mode as well.Anton Korobeynikov2012-08-181-4/+4
| | | | | | Make sure the generic pattern is used. llvm-svn: 162170
* Avoid folding ADD instructions with FI operands.Jakob Stoklund Olesen2012-08-171-0/+3
| | | | | | | | | PEI can't handle the pseudo-instructions. This can be removed when the pseudo-instructions are replaced by normal predicated instructions. Fixes PR13628. llvm-svn: 162130
* Add comment, clean up code. No functional change.Jakob Stoklund Olesen2012-08-171-30/+39
| | | | llvm-svn: 162107
* Implement NEON domain switching for scalar <-> S-register vmovs on ARMTim Northover2012-08-171-15/+97
| | | | llvm-svn: 162094
* Remove unnecessary include of ARMGenInstrInfo.inc.Craig Topper2012-08-171-1/+0
| | | | llvm-svn: 162086
* Add ADD and SUB to the predicable ARM instructions.Jakob Stoklund Olesen2012-08-163-0/+51
| | | | | | | | | | It is not my plan to duplicate the entire ARM instruction set with predicated versions. We need a way of representing predicated instructions in SSA form without requiring a separate opcode. Then the pseudo-instructions can go away. llvm-svn: 162061
* Handle ARM MOVCC optimization in PeepholeOptimizer.Jakob Stoklund Olesen2012-08-165-53/+73
| | | | | | Use the target independent select analysis hooks. llvm-svn: 162060
* [arm-fast-isel] Add support for fastcc.Jush Lu2012-08-161-3/+6
| | | | | | | | Without fastcc support, the caller just falls through to CallingConv::C for fastcc, but callee still uses fastcc, this inconsistency of calling convention is a problem, and fastcc support can fix it. llvm-svn: 162013
* Fold predicable instructions into MOVCC / t2MOVCC.Jakob Stoklund Olesen2012-08-155-2/+104
| | | | | | | | | | | | | | The ARM select instructions are just predicated moves. If the select is the only use of an operand, the instruction defining the operand can be predicated instead, saving one instruction and decreasing register pressure. This implementation can turn AND/ORR/EOR instructions into their corresponding ANDCC/ORRCC/EORCC variants. Ideally, we should be able to predicate any instruction, but we don't yet support predicated instructions in SSA form. llvm-svn: 161994
* Use vld1/vst1 to load/store f64 if alignment is < 4 and the target allows ↵Evan Cheng2012-08-154-2/+50
| | | | | | unaligned access. rdar://12091029 llvm-svn: 161962
* Add missing Rfalse operand to the predicated pseudo-instructions.Jakob Stoklund Olesen2012-08-153-28/+41
| | | | | | | | | | | | | | | | | | | | | | | When predicating this instruction: Rd = ADD Rn, Rm We need an extra operand to represent the value given to Rd when the predicate is false: Rd = ADDCC Rfalse, Rn, Rm, pred The Rd and Rfalse operands are different registers while in SSA form. Rfalse is tied to Rd to make sure they get the same register during register allocation. Previously, Rd and Rn were tied, but that is not required. Compare to MOVCC: Rd = MOVCC Rfalse, Rtrue, pred llvm-svn: 161955
* The names of VFP variants of half-to-float conversion instructions wereAnton Korobeynikov2012-08-141-7/+7
| | | | | | | | reversed. This leads to wrong codegen for float-to-half conversion intrinsics which are used to support storage-only fp16 type. NEON variants of same instructions are fine. llvm-svn: 161907
* This needs braces. Spotted by Bill.Eric Christopher2012-08-141-1/+2
| | | | llvm-svn: 161906
* Switch the fixed-length disassembler to be table-driven.Jim Grosbach2012-08-141-411/+425
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. llvm-svn: 161888
* Remove the TII::scheduleTwoAddrSource() hook.Jakob Stoklund Olesen2012-08-132-47/+0
| | | | | | | | | | | | | | | It never does anything when running 'make check', and it get's in the way of updating live intervals in 2-addr. The hook was originally added to help form IT blocks in Thumb2 code before register allocation, but the pass ordering has changed since then, and we run if-conversion after register allocation now. When the MI scheduler is enabled, there will be no less than two schedulers between 2-addr and Thumb2ITBlockPass, so this hook is unlikely to help anything. llvm-svn: 161794
* ARM: enable struct byval for AAPCS-VFP.Manman Ren2012-08-131-0/+3
| | | | | | | | This change is to be enabled in clang. rdar://9877866 llvm-svn: 161789
* Do not optimize (or (and X,Y), Z) into BFI and other sequences if the AND ↵Nadav Rotem2012-08-131-1/+5
| | | | | | | | ISDNode has more than one user. rdar://11876519 llvm-svn: 161775
* Add support for the %H output modifier.Eric Christopher2012-08-131-2/+15
| | | | | | Patch by Weiming Zhao. llvm-svn: 161768
* Use correct loads for vector types during extending-load operations.Tim Northover2012-08-131-36/+36
| | | | | | | | Previously, we used VLD1.32 in all cases, however there are both 16 and 64-bit accesses being selected, so we need to use an appropriate width load in those cases. llvm-svn: 161748
* Revert 161581: Patch to implement UMLAL/SMLAL instructions for the ARMArnold Schwaighofer2012-08-125-251/+17
| | | | | | | | | architecture It broke MultiSource/Applications/JM/ldecod/ldecod on armv7 thumb O0 g and armv7 thumb O3. llvm-svn: 161736
* Change addTypeForNeon to use MVT instead of EVT so all the calls to ↵Craig Topper2012-08-122-51/+46
| | | | | | getSimpleVT can be removed. llvm-svn: 161735
* ARM: enable struct byval for AAPCS.Manman Ren2012-08-101-0/+3
| | | | | | | | | This change is to be enabled in clang. rdar://9877866 PR://13350 llvm-svn: 161693
* Remove getARMRegisterNumbering and replace with calls intoEric Christopher2012-08-097-154/+90
| | | | | | | | | | | the register info for getEncodingValue. This builds on the small patch of yesterday to set HWEncoding in the register file. One (deprecated) use was turned into a hard number to avoid needing register info in the old JIT. llvm-svn: 161628
* Patch to implement UMLAL/SMLAL instructions for the ARM architectureArnold Schwaighofer2012-08-095-17/+251
| | | | | | | | | | | This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! llvm-svn: 161581
* This field isn't used anymore, use it with HWEncoding instead.Eric Christopher2012-08-091-4/+4
| | | | llvm-svn: 161564
* Added MispredictPenalty to SchedMachineModel.Andrew Trick2012-08-084-9/+9
| | | | | | | This replaces an existing subtarget hook on ARM and allows standard CodeGen passes to potentially use the property. llvm-svn: 161471
* whitespaceAndrew Trick2012-08-081-1/+1
| | | | llvm-svn: 161469
* Skip impdef regs during eabi save/restore list emission to workaround PR11902Anton Korobeynikov2012-08-041-2/+8
| | | | llvm-svn: 161301
* Recognize vst1.64 / vld1.64 with 3 and 4 regs as load from / store to stack ↵Anton Korobeynikov2012-08-041-0/+4
| | | | | | | | | stuff (this corresponds by spilling/reloading regs in DTriple / DQuad reg classes). No testcase, found by inspection. llvm-svn: 161300
* Add stack spill / reload instructions for DTriple and DQuad register ↵Anton Korobeynikov2012-08-041-3/+43
| | | | | | | | classes, which were missed for no reason. This fixes PR13377 llvm-svn: 161299
* Fall back to selection DAG isel for calls to builtin functions.Bob Wilson2012-08-033-8/+13
| | | | | | | | | | Fast isel doesn't currently have support for translating builtin function calls to target instructions. For embedded environments where the library functions are not available, this is a matter of correctness and not just optimization. Most of this patch is just arranging to make the TargetLibraryInfo available in fast isel. <rdar://problem/12008746> llvm-svn: 161232
* [arm-fast-isel] Add support for shl, lshr, and ashr.Jush Lu2012-08-031-0/+62
| | | | llvm-svn: 161230
* Add support for the ARM GHC calling convention, this patch was in 3.0,Eric Christopher2012-08-035-0/+54
| | | | | | | | but somehow managed to be dropped later. Patch by Karel Gardas. llvm-svn: 161226
* ARM: Tidy up. Remove unused template parameters.Jim Grosbach2012-08-021-20/+16
| | | | llvm-svn: 161222
* ARM: More InstAlias refactors to use #NAME#.Jim Grosbach2012-08-021-42/+27
| | | | llvm-svn: 161220
* ARM: Refactor instaliases using TableGen support for #NAME#.Jim Grosbach2012-08-021-31/+23
| | | | | | | | Now that TableGen supports references to NAME w/o it being explicitly referenced in the definition's own name, use that to simplify assembly InstAlias definitions in multiclasses. llvm-svn: 161218
* Support fpv4 for ARM Cortex-M4.Jiangning Liu2012-08-021-1/+1
| | | | llvm-svn: 161163
* Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset ↵Jiangning Liu2012-08-023-16/+29
| | | | | | index issue. llvm-svn: 161162
* Fix #13138, a bug around ARM instruction DSB encoding and decoding issue.Jiangning Liu2012-08-023-40/+75
| | | | llvm-svn: 161161
* Fix #13241, a bug around shift immediate operand for ARM instruction ADR.Jiangning Liu2012-08-026-7/+64
| | | | llvm-svn: 161159
* ARM: Remove redundant instalias.Jim Grosbach2012-08-011-3/+0
| | | | llvm-svn: 161134
* Clean up formatting.Jim Grosbach2012-08-012-13/+2
| | | | llvm-svn: 161133
* Tidy up.Jim Grosbach2012-08-011-11/+4
| | | | llvm-svn: 161132
* Fix a bug in ARMMachObjectWriter::RecordRelocation() in ARMMachObjectWriter.cppKevin Enderby2012-07-301-2/+9
| | | | | | | | | where the other_half of the movt and movw relocation entries needs to get set and only with the 16 bits of the other half. rdar://10038370 llvm-svn: 160978
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