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* ARM: Don't assume an SDNode is a constant.Jim Grosbach2012-07-251-0/+4
| | | | | | | | | Before accessing a node as a ConstandSDNode, make sure it actually is one. No testcase of non-trivial size. rdar://11948669 llvm-svn: 160735
* Fix a typo (the the => the)Sylvestre Ledru2012-07-233-3/+3
| | | | llvm-svn: 160621
* [arm-fast-isel] Add support for vararg function calls.Jush Lu2012-07-191-28/+36
| | | | llvm-svn: 160500
* Fix ARMTargetLowering::isLegalAddImmediate to consider thumb encodings.Andrew Trick2012-07-181-4/+11
| | | | | | Based on Evan's suggestion without a commitable test. llvm-svn: 160441
* whitespaceAndrew Trick2012-07-181-2/+2
| | | | llvm-svn: 160440
* More replacing of target-dependent intrinsics with target-indepdent Joel Jones2012-07-181-2/+2
| | | | | | | | | | | | | | | | | | | | | intrinsics. The second instruction(s) to be handled are the vector versions of count set bits (ctpop). The changes here are to clang so that it generates a target independent vector ctpop when it sees an ARM dependent vector bits set count. The changes in llvm are to match the target independent vector ctpop and in VMCore/AutoUpgrade.cpp to update any existing bc files containing ARM dependent vector pop counts with target-independent ctpops. There are also changes to an existing test case in llvm for ARM vector count instructions and to a test for the bitcode upgrade. <rdar://problem/11892519> There is deliberately no test for the change to clang, as so far as I know, no consensus has been reached regarding how to test neon instructions in clang; q.v. <rdar://problem/8762292> llvm-svn: 160410
* This is one of the first steps at moving to replace target-dependent Joel Jones2012-07-131-1/+1
| | | | | | | | | | | | | | | | | | | | intrinsics with target-indepdent intrinsics. The first instruction(s) to be handled are the vector versions of count leading zeros (ctlz). The changes here are to clang so that it generates a target independent vector ctlz when it sees an ARM dependent vector ctlz. The changes in llvm are to match the target independent vector ctlz and in VMCore/AutoUpgrade.cpp to update any existing bc files containing ARM dependent vector ctlzs with target-independent ctlzs. There are also changes to an existing test case in llvm for ARM vector count instructions and a new test for the bitcode upgrade. <rdar://problem/11831778> There is deliberately no test for the change to clang, as so far as I know, no consensus has been reached regarding how to test neon instructions in clang; q.v. <rdar://problem/8762292> llvm-svn: 160200
* Remove variable_ops from ARM call instructions.Jakob Stoklund Olesen2012-07-133-22/+19
| | | | | | | | | | | | Function argument registers are added to the call SDNode, but InstrEmitter now knows how to make those operands implicit, and the call instruction doesn't have to be variadic. Explicit register operands should only be those that are encoded in the instruction, implicit register operands are for extra dependencies like call argument and return values. llvm-svn: 160188
* ARM: fix typo in commentsManman Ren2012-07-111-1/+1
| | | | llvm-svn: 160093
* ARM: Fix optimizeCompare to correctly check safe condition.Manman Ren2012-07-111-9/+14
| | | | | | | | It is safe if CPSR is killed or re-defined. When we are done with the basic block, check whether CPSR is live-out. Do not optimize away cmp if CPSR is live-out. llvm-svn: 160090
* Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton2012-07-102-8/+8
| | | | | | single-precision resiters) (and do it properly this time! llvm-svn: 159989
* ARM: Allow more flexible patterns in NEON formats.Jim Grosbach2012-07-101-53/+53
| | | | | | | | | Some NEON instructions want to match against normal SDNodes for some operand types and Intrinsics for others. For example, CTLZ. To enable this, switch from explicitly requiring Intrinsic on the class templates to using SDPatternOperator instead. llvm-svn: 159974
* Revert r159938 (and r159945) to appease the buildbots.Chad Rosier2012-07-092-8/+8
| | | | llvm-svn: 159960
* Some formatting to keep Clang happyRichard Barton2012-07-091-4/+4
| | | | llvm-svn: 159948
* Oops - correct broken disassembly for VMOVRichard Barton2012-07-091-1/+1
| | | | llvm-svn: 159945
* Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton2012-07-092-8/+8
| | | | | | single-precision resiters) llvm-svn: 159938
* Prevent ARM assembler from losing a right shift by #32 applied to a registerRichard Barton2012-07-091-1/+3
| | | | llvm-svn: 159937
* Spelling!Richard Barton2012-07-091-2/+2
| | | | llvm-svn: 159936
* Teach the assembler to use the narrow thumb encodings of various ↵Richard Barton2012-07-091-0/+80
| | | | | | three-register dp instructions where permissable. llvm-svn: 159935
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-073-13/+42
| | | | | | | | | | | | | | | | | | | | | | | subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
* Fix the naming of ensureAlignment. Per the coding standard function namesChad Rosier2012-07-061-3/+3
| | | | | | should be camel case, and start with a lower case letter. llvm-svn: 159877
* ARM: Add test cleanup entry to the README.Jim Grosbach2012-07-061-0/+21
| | | | llvm-svn: 159864
* Revert r159804, "[arm-fast-isel] Add support for vararg function calls."NAKAMURA Takumi2012-07-061-33/+26
| | | | | | It broke LLVM :: CodeGen/Thumb2/large-call.ll on several hosts. llvm-svn: 159817
* [arm-fast-isel] Add support for vararg function calls.Jush Lu2012-07-061-26/+33
| | | | llvm-svn: 159804
* Consistently use AnalysisID types in TargetPassConfig.Bob Wilson2012-07-021-2/+2
| | | | | | | This makes it possible to just use a zero value to represent "no pass", so the phony NoPassID global variable is no longer needed. llvm-svn: 159568
* Add all codegen passes to the PassManager via TargetPassConfig.Bob Wilson2012-07-021-10/+10
| | | | | | | | This is a preliminary step toward having TargetPassConfig be able to start and stop the compilation at specified passes for unit testing and debugging. No functionality change. llvm-svn: 159567
* Revert accidental checkin.Andrew Trick2012-07-021-3/+2
| | | | | | My last checkin was apparently not the branch I intended. It was missing one change (added by chandlerc), and contained a spurious change. llvm-svn: 159548
* Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick2012-07-024-48/+64
| | | | | | Reapplies r159406 with minor cleanup. The regressions appear to have been spurious. llvm-svn: 159541
* Do not attempt to use ROR for Thumb1.Bob Wilson2012-07-021-2/+2
| | | | | | Patch by Matt Fischer! llvm-svn: 159538
* ARM: Clean up optimizeCompare in peephole, no functional change.Manman Ren2012-06-291-80/+73
| | | | | | | | Use getUniqueVRegDef. Replace a loop with existing interfaces: modifiesRegister and readsRegister. Factor out code into inline functions and simplify the code. llvm-svn: 159470
* Add SrcReg2 to analyzeCompare and optimizeCompareInstr to handle CompareManman Ren2012-06-292-24/+35
| | | | | | instructions with two register operands. llvm-svn: 159465
* Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick2012-06-294-62/+47
| | | | | | This reverts commit r159406. I noticed a performance regression so I'll back out for now. llvm-svn: 159411
* Make NumMicroOps a variable in the subtarget's instruction itinerary.Andrew Trick2012-06-294-47/+62
| | | | | | | | | | | | | | The TargetInstrInfo::getNumMicroOps API does not change, but soon it will be used by MachineScheduler. Now each subtarget can specify the number of micro-ops per itinerary class. For ARM, this is currently always dynamic (-1), because it is used for load/store multiple which depends on the number of register operands. Zero is now a valid number of micro-ops. This can be used for nop pseudo-instructions or instructions that the hardware can squash during dispatch. llvm-svn: 159406
* Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp andBill Wendling2012-06-281-1/+1
| | | | | | | | | include/llvm/Analysis/DebugInfo.h to include/llvm/DebugInfo.h. The reasoning is because the DebugInfo module is simply an interface to the debug info MDNodes and has nothing to do with analysis. llvm-svn: 159312
* Teach assembler to handle capitalised operation values for DSB instructionsRichard Barton2012-06-271-1/+1
| | | | llvm-svn: 159259
* Prevent ARM Assembler crashing on unrecognised assembly format for DSB ↵Richard Barton2012-06-271-1/+2
| | | | | | instruction llvm-svn: 159257
* Add a missing check to avoid dereference null. No sensible test case ↵Evan Cheng2012-06-261-0/+2
| | | | | | possible. Sorry. rdar://11745134 llvm-svn: 159236
* There are a number of generic inline asm operand modifiers thatJack Carter2012-06-261-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | up to r158925 were handled as processor specific. Making them generic and putting tests for these modifiers in the CodeGen/Generic directory caused a number of targets to fail. This commit addresses that problem by having the targets call the generic routine for generic modifiers that they don't currently have explicit code for. For now only generic print operands 'c' and 'n' are supported.vi Affected files: test/CodeGen/Generic/asm-large-immediate.ll lib/Target/PowerPC/PPCAsmPrinter.cpp lib/Target/NVPTX/NVPTXAsmPrinter.cpp lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/XCore/XCoreAsmPrinter.cpp lib/Target/X86/X86AsmPrinter.cpp lib/Target/Hexagon/HexagonAsmPrinter.cpp lib/Target/CellSPU/SPUAsmPrinter.cpp lib/Target/Sparc/SparcAsmPrinter.cpp lib/Target/MBlaze/MBlazeAsmPrinter.cpp lib/Target/Mips/MipsAsmPrinter.cpp MSP430 isn't represented because it did not even run with the long existing 'c' modifier and it was not apparent what needs to be done to get it inline asm ready. Contributer: Jack Carter llvm-svn: 159203
* ARM: update peephole optimization.Manman Ren2012-06-251-2/+18
| | | | | | | | | | More condition codes are included when deciding whether to remove cmp after a sub instruction. Specifically, we extend from GE|LT|GT|LE to GE|LT|GT|LE|HS|LS|HI|LO|EQ|NE. If we have "sub a, b; cmp b, a; movhs", we should be able to replace with "sub a, b; movls". rdar: 11725965 llvm-svn: 159166
* llvm/lib: [CMake] Add explicit dependency to intrinsics_gen.NAKAMURA Takumi2012-06-241-0/+2
| | | | llvm-svn: 159112
* (sub X, imm) gets canonicalized to (add X, -imm)Evan Cheng2012-06-233-7/+21
| | | | | | | | | | | | | | | There are patterns to handle immediates when they fit in the immediate field. e.g. %sub = add i32 %x, -123 => sub r0, r0, #123 Add patterns to catch immediates that do not fit but should be materialized with a single movw instruction rather than movw + movt pair. e.g. %sub = add i32 %x, -65535 => movw r1, #65535 sub r0, r0, r1 rdar://11726136 llvm-svn: 159057
* ARM: Add a better diagnostic for some out of range immediates.Jim Grosbach2012-06-222-2/+13
| | | | | | | | | | | As an example of how the custom DiagnosticType can be used to provide better operand-mismatch diagnostics, add a custom diagnostic for the imm0_15 operand class used for several system instructions. Update the tests to expect the improved diagnostic. rdar://8987109 llvm-svn: 159051
* Use "NoItineraries" for processors with no itineraries.Andrew Trick2012-06-222-3/+1
| | | | | | | | This makes it explicit when ScoreboardHazardRecognizer will be used. "GenericItineraries" would only make sense if it contained real itinerary values and still required ScoreboardHazardRecognizer. llvm-svn: 158963
* ARM scheduling fix: don't guess at implicit operand latency.Andrew Trick2012-06-221-5/+9
| | | | | | | | | | This is a minor drive-by fix with no robust way to unit test. As an example see neon-div.ll: SU(16): %Q8<def> = VMOVLsv4i32 %D17, pred:14, pred:%noreg, %Q8<imp-use,kill> val SU(1): Latency=2 Reg=%Q8 ...should be latency=1 llvm-svn: 158960
* ARM scheduling fix: compute predicated implicit use properly.Andrew Trick2012-06-221-3/+1
| | | | | | | | Minor drive by fix to cleanup latency computation. Calling getOperandLatency with a deliberately incorrect operand index does not give you the latency you want. llvm-svn: 158959
* Rename -allow-excess-fp-precision flag to -fuse-fp-ops, and switch from aLang Hames2012-06-221-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | boolean flag to an enum: { Fast, Standard, Strict } (default = Standard). This option controls the creation by optimizations of fused FP ops that store intermediate results in higher precision than IEEE allows (E.g. FMAs). The behavior of this option is intended to match the behaviour specified by a soon-to-be-introduced frontend flag: '-ffuse-fp-ops'. Fast mode - allows formation of fused FP ops whenever they're profitable. Standard mode - allow fusion only for 'blessed' FP ops. At present the only blessed op is the fmuladd intrinsic. In the future more blessed ops may be added. Strict mode - allow fusion only if/when it can be proven that the excess precision won't effect the result. Note: This option only controls formation of fused ops by the optimizers. Fused operations that are explicitly requested (e.g. FMA via the llvm.fma.* intrinsic) will always be honored, regardless of the value of this option. Internally TargetOptions::AllowExcessFPPrecision has been replaced by TargetOptions::AllowFPOpFusion. llvm-svn: 158956
* Add a missing llvm.fma -> VFNMS pattern to the ARM backend.Lang Hames2012-06-211-0/+8
| | | | llvm-svn: 158902
* Add DAG-combines for aggressive FMA formation.Lang Hames2012-06-191-1/+1
| | | | | | | | | | | | | | | | | | | | This patch adds DAG combines to form FMAs from pairs of FADD + FMUL or FSUB + FMUL. The combines are performed when: (a) Either AllowExcessFPPrecision option (-enable-excess-fp-precision for llc) OR UnsafeFPMath option (-enable-unsafe-fp-math) are set, and (b) TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) is true for the type of the FADD/FSUB, and (c) The FMUL only has one user (the FADD/FSUB). If your target has fast FMA instructions you can make use of these combines by overriding TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) to return true for types supported by your FMA instruction, and adding patterns to match ISD::FMA to your FMA instructions. llvm-svn: 158757
* Have ARM ELF use correct reloc for "b" instr.Jan Wen Voung2012-06-191-5/+3
| | | | | | | The condition code didn't actually matter for arm "b" instructions, unlike "bl". It should just use the R_ARM_JUMP24 reloc. llvm-svn: 158722
* Move the support for using .init_array from ARM to the genericRafael Espindola2012-06-192-45/+2
| | | | | | | | | | TargetLoweringObjectFileELF. Use this to support it on X86. Unlike ARM, on X86 it is not easy to find out if .init_array should be used or not, so the decision is made via TargetOptions and defaults to off. Add a command line option to llc that enables it. llvm-svn: 158692
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