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* Conditional moves are slightly more expensive than moves.Evan Cheng2010-11-136-10/+11
| | | | llvm-svn: 118985
* Add conditional move of large immediate.Evan Cheng2010-11-134-18/+47
| | | | llvm-svn: 118968
* Swap multiclass operand order for consistency with other patterns.Jim Grosbach2010-11-131-3/+3
| | | | llvm-svn: 118965
* Continue ARM indexed load refactoring. Multiclass for LDR{B} pre/post indexedJim Grosbach2010-11-131-18/+12
| | | | | | instructions. llvm-svn: 118963
* More ARM load/store indexed refactoring. Also fix an incorrect IndexModeJim Grosbach2010-11-132-75/+54
| | | | | | flag for the LDRT/STRT family instructions as a side effect. llvm-svn: 118955
* Fix an obvious typo which inverted an immediate.Evan Cheng2010-11-131-1/+1
| | | | llvm-svn: 118951
* Temporarily revert this.Eric Christopher2010-11-121-5/+4
| | | | llvm-svn: 118946
* For pre-v6t2 targets, only select MOVi32imm if the immediate can be handled ↵Evan Cheng2010-11-123-15/+11
| | | | | | with movi + orr. llvm-svn: 118945
* Revert r118939 while I work out why it broke some buildbots.Owen Anderson2010-11-121-65/+52
| | | | llvm-svn: 118942
* Attemt to provide correct encodings for Thumb2 binary operators.Owen Anderson2010-11-121-52/+65
| | | | llvm-svn: 118939
* Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either ↵Evan Cheng2010-11-125-72/+34
| | | | | | movi+orr or movw+movt depending on the subtarget. llvm-svn: 118938
* Make this happen for ARM like x86. Don't entirely bail out whenEric Christopher2010-11-121-4/+5
| | | | | | | an address is in a different block, get it into a register and go from there. llvm-svn: 118936
* Add conditional mvn instructions.Evan Cheng2010-11-123-10/+67
| | | | llvm-svn: 118935
* Zap a copy/paste-o bit of dead code.Jim Grosbach2010-11-121-2/+0
| | | | llvm-svn: 118926
* Refactor to parameterize some ARM load/store encoding patterns. PreparatoryJim Grosbach2010-11-122-86/+24
| | | | | | | to splitting the load/store pre/post indexed instructions into [r, r] and [r, imm] forms. llvm-svn: 118925
* First stab at providing correct Thumb2 encodings, start with adc.Owen Anderson2010-11-123-19/+122
| | | | llvm-svn: 118924
* Add some missing isel predicates on def : pat patterns to avoid generating ↵Evan Cheng2010-11-123-64/+54
| | | | | | VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next. llvm-svn: 118922
* Kill more unused stuff.Jim Grosbach2010-11-121-43/+0
| | | | llvm-svn: 118921
* Remove unused class.Jim Grosbach2010-11-121-8/+0
| | | | llvm-svn: 118919
* Fill in the default predication bits for ARM unconditional branch.Jim Grosbach2010-11-121-0/+1
| | | | llvm-svn: 118907
* Encoding for ARM LDRSB instructions.Jim Grosbach2010-11-121-7/+12
| | | | llvm-svn: 118905
* Fix up a few more spots of addrmode2 (or not) changes that wereEric Christopher2010-11-121-6/+12
| | | | | | | | missed. Update some comments accordingly. Fixes rdar://8652289 llvm-svn: 118888
* Start of support for binary emit of 16-it Thumb instructions.Jim Grosbach2010-11-112-7/+18
| | | | llvm-svn: 118859
* Fill out support for Thumb2 encodings of NEON instructions.Owen Anderson2010-11-113-0/+21
| | | | llvm-svn: 118854
* Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4].Owen Anderson2010-11-113-1/+22
| | | | llvm-svn: 118843
* Revert the accidental commit I made reverting the previous commit.Eric Christopher2010-11-111-6/+7
| | | | llvm-svn: 118835
* ARM fixup encoding for direct call instructions (BL).Jim Grosbach2010-11-111-8/+22
| | | | llvm-svn: 118829
* Revert this temporarily.Eric Christopher2010-11-115-104/+31
| | | | llvm-svn: 118827
* Change the prologue and epilogue to use push/pop for the low ARM registers.Eric Christopher2010-11-114-25/+97
| | | | llvm-svn: 118823
* Add support for Thumb2 encodings of NEON data processing instructions, using ↵Owen Anderson2010-11-113-0/+26
| | | | | | | | the new PostEncoderMethod infrastructure. More tests to come. llvm-svn: 118819
* Encoding of destination fixup for ARM branch and conditional branchJim Grosbach2010-11-115-13/+57
| | | | | | instructions. llvm-svn: 118801
* Encoding for ARM LDRSH_POST.Jim Grosbach2010-11-114-7/+39
| | | | llvm-svn: 118794
* Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names.Jim Grosbach2010-11-112-39/+49
| | | | llvm-svn: 118767
* Fix encoding of Ra register for ARM smla* instructions.Jim Grosbach2010-11-111-6/+6
| | | | llvm-svn: 118761
* ARM STRH encoding information.Jim Grosbach2010-11-114-11/+44
| | | | llvm-svn: 118757
* Move LDM predicate operand encoding into base clase. Add STM missing STMJim Grosbach2010-11-102-10/+18
| | | | | | encoding bits. llvm-svn: 118738
* ARM LDM encoding for the mode (ia, ib, da, db) operand.Jim Grosbach2010-11-104-1/+19
| | | | llvm-svn: 118736
* Fix ARM encoding of non-return LDM instructions.Jim Grosbach2010-11-102-4/+11
| | | | llvm-svn: 118732
* Fix ARM encoding of LDM+Return instruction.Jim Grosbach2010-11-102-3/+10
| | | | llvm-svn: 118730
* Fix an issue where we tried to turn a v2f32 build_vector into a v4i32 build ↵Nate Begeman2010-11-101-2/+2
| | | | | | vector with 2 elts llvm-svn: 118720
* Simplify and clean up MC symbol lookup for ARM constant pool values. This fixesJim Grosbach2010-11-101-10/+10
| | | | | | | | double quoting of ObjC symbol names in constant pool entries. rdar://8652107 llvm-svn: 118688
* Update ARMConstantPoolValue to not use a modifier string. Use an explicitJim Grosbach2010-11-101-47/+38
| | | | | | | VariantKind marker to indicate the additional information necessary. Update MC to handle the new Kinds. rdar://8647623 llvm-svn: 118671
* Emit a '!' if this is a "writeback" register or memory address.Bill Wendling2010-11-101-2/+2
| | | | llvm-svn: 118662
* Rename a parameter to avoid confusion with a local variableMatt Beaumont-Gay2010-11-101-3/+3
| | | | llvm-svn: 118656
* Emit the warning about the register list not being in ascending order only once.Bill Wendling2010-11-091-5/+8
| | | | llvm-svn: 118653
* s/std::vector/SmallVector/Bill Wendling2010-11-091-12/+11
| | | | llvm-svn: 118648
* Delete the allocated vector.Bill Wendling2010-11-091-0/+4
| | | | llvm-svn: 118644
* Define the subtarget feature for the architecture version,Bob Wilson2010-11-091-15/+40
| | | | | | | as derived from the target triple. This is important for enabling features that are implied based on the architecture version. llvm-svn: 118643
* Do not use MEMBARRIER_MCR for any Thumb code.Bob Wilson2010-11-091-2/+2
| | | | | | | | | It is only supported for ARM code. Normally Thumb2 code would use DMB instead, but depending on how the compiler is invoked (e.g., -mattr=-db) that might be disabled. This prevents a "cannot select MEMBARRIER_MCR" error in that situation. Radar 8644195 llvm-svn: 118642
* Two types of instructions have register lists:Bill Wendling2010-11-091-56/+32
| | | | | | | | | | | * LDM, et al, uses a bit mask to indicate the register list. * VLDM, et al, uses a base register plus number. The LDM instructions may be non-contiguous, but the VLDM ones must be contiguous. Those are semantic checks that should be done later in the compiler. Also postpone the creation of the bit mask until it's needed. llvm-svn: 118640
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