summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM
Commit message (Collapse)AuthorAgeFilesLines
...
* Remove autoconf supportChris Bieneman2016-01-266-101/+0
| | | | | | | | | | | | | | | | Summary: This patch is provided in preparation for removing autoconf on 1/26. The proposal to remove autoconf on 1/26 was discussed on the llvm-dev thread here: http://lists.llvm.org/pipermail/llvm-dev/2016-January/093875.html "I felt a great disturbance in the [build system], as if millions of [makefiles] suddenly cried out in terror and were suddenly silenced. I fear something [amazing] has happened." - Obi Wan Kenobi Reviewers: chandlerc, grosbach, bob.wilson, tstellarAMD, echristo, whitequark Subscribers: chfast, simoncook, emaste, jholewinski, tberghammer, jfb, danalbert, srhines, arsenm, dschuff, jyknight, dsanders, joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D16471 llvm-svn: 258861
* Reflect the MC/MCDisassembler split on the include/ level.Benjamin Kramer2016-01-263-3/+3
| | | | | | No functional change, just moving code around. llvm-svn: 258818
* [ARM] Add DSP build attribute and extension targetingBradley Smith2016-01-251-0/+3
| | | | | | | | This patch was originally committed as r257885, but was reverted due to windows failures. The cause of these failures has been fixed under r258677, hence re-committing the original patch. llvm-svn: 258683
* [ARM] Add new system registers to ARMv8-M Baseline/MainlineBradley Smith2016-01-254-7/+112
| | | | | | | | This patch was originally committed as r257884, but was reverted due to windows failures. The cause of these failures has been fixed under r258677, hence re-committing the original patch. llvm-svn: 258682
* [ARM] Add ARMv8-M security extension instructions to ARMv8-M Baseline/MainlineBradley Smith2016-01-258-1/+95
| | | | | | | | This patch was originally committed as r257883, but was reverted due to windows failures. The cause of these failures has been fixed under r258677, hence re-committing the original patch. llvm-svn: 258681
* [ARM] Add ARMv8.2-A FP16 scalar instructionsOliver Stannard2016-01-2512-6/+784
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was originally committed as r255762, but reverted as it broke windows bots. Re-commitiing the exact same patch, as the underlying cause was fixed by r258677. ARMv8.2-A adds 16-bit floating point versions of all existing VFP floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. The assembly for these instructions uses S registers (AArch32 does not have H registers), but the instructions have ".f16" type specifiers rather than ".f32" or ".f64". The top 16 bits of each source register are ignored, and the top 16 bits of the destination register are set to zero. These instructions are mostly the same as the 32- and 64-bit versions, but they use coprocessor 9 rather than 10 and 11. Two new instructions, VMOVX and VINS, have been added to allow packing and extracting two 16-bit floats stored in the top and bottom halves of an S register. New fixup kinds have been added for the PC-relative load and store instructions, but no ELF relocations have been added as they have a range of 512 bytes. Differential Revision: http://reviews.llvm.org/D15038 llvm-svn: 258678
* [ARM] Operands for PKHTB alias should be swappedOliver Stannard2016-01-182-6/+6
| | | | | | | | | When the shift immediate is zero, PKHTB is an alias for PKHBT, but the order of the input operands needs to be swapped. Differential Revision: http://reviews.llvm.org/D16288 llvm-svn: 258044
* [opaque pointer types] [NFC] CallSite: use getFunctionType() instead of ↵Manuel Jacob2016-01-171-2/+1
| | | | | | | | | | | | | | going through PointerType::getElementType. Patch by Eduard Burtescu. Reviewers: dblaikie, mjacob Subscribers: dsanders, llvm-commits, dblaikie Differential Revision: http://reviews.llvm.org/D16273 llvm-svn: 258023
* CXX_FAST_TLS calling convention: fix issue on ARM.Manman Ren2016-01-151-4/+5
| | | | | | | | | | When we have a single basic block, the explicit copy-back instructions should be inserted right before the terminator. Before this fix, they were wrongly placed at the beginning of the basic block. PR26136 llvm-svn: 257930
* Revert "[ARM] Add ARMv8-M security extension instructions to ARMv8-M ↵Reid Kleckner2016-01-158-94/+1
| | | | | | | | | | Baseline/Mainline" This reverts commit r257883. Somehow this didn't make it into r257916. llvm-svn: 257919
* # This is a combination of 2 commits.Reid Kleckner2016-01-155-115/+7
| | | | | | | | | | | | | | | | # The first commit's message is: Revert "[ARM] Add DSP build attribute and extension targeting" This reverts commit b11cc50c0b4a7c8cdb628abc50b7dc226ff583dc. # This is the 2nd commit message: Revert "[ARM] Add new system registers to ARMv8-M Baseline/Mainline" This reverts commit 837d08454e3e5beb8581951ac26b22fa07df3cd5. llvm-svn: 257916
* [ARM] Add DSP build attribute and extension targetingBradley Smith2016-01-151-0/+3
| | | | llvm-svn: 257885
* [ARM] Add new system registers to ARMv8-M Baseline/MainlineBradley Smith2016-01-154-7/+112
| | | | llvm-svn: 257884
* [ARM] Add ARMv8-M security extension instructions to ARMv8-M Baseline/MainlineBradley Smith2016-01-158-1/+94
| | | | llvm-svn: 257883
* [ARM] Add ARMv8-A semaphore/atomic instructions to ARMv8-M Baseline/MainlineBradley Smith2016-01-155-14/+25
| | | | llvm-svn: 257882
* [ARM] Add B.W and CBZ instructions to ARMv8-M BaselineBradley Smith2016-01-155-11/+23
| | | | llvm-svn: 257881
* [ARM] Add SDIV/UDIV instructions to ARMv8-M BaselineBradley Smith2016-01-152-4/+5
| | | | llvm-svn: 257880
* [ARM] Add MOVW/MOVT instructions to ARMv8-M Baseline/MainlineBradley Smith2016-01-153-12/+15
| | | | llvm-svn: 257879
* [ARM] Add ARMv8-M Baseline/Mainline LLVM targetingBradley Smith2016-01-156-5/+59
| | | | llvm-svn: 257878
* [ARM] Split out ARMv8-A semaphores and atomics and ARMv7 clrex as separate ↵Bradley Smith2016-01-156-22/+53
| | | | | | features llvm-svn: 257877
* Update to use new name alignTo().Rui Ueyama2016-01-142-2/+2
| | | | llvm-svn: 257804
* [ARM] Use the efficient version of BitVector::set and a static_assert.Benjamin Kramer2016-01-141-3/+2
| | | | | | No functional change intended. llvm-svn: 257766
* Convert a few assert failures into proper errors.Rafael Espindola2016-01-131-3/+3
| | | | | | Fixes PR25944. llvm-svn: 257697
* Guard fabs to bfc convert with V6T2 flagAna Pazos2016-01-131-2/+2
| | | | | | | | | | | | | | Summary: BFC instructions are available in ARMv6T2 and above. Reviewers: t.p.northover Subscribers: aemerson Differential Revision: http://reviews.llvm.org/D16076 llvm-svn: 257546
* [ARM] Mark VMOV with immediate: isAsCheapAsMove.Quentin Colombet2016-01-131-2/+5
| | | | | | | | | | VMOVs are not strictly speaking cheap, but they are as expensive as a vector copy (VORR), so we should prefer rematerialization over splitting when it applies. rdar://problem/23754176 llvm-svn: 257545
* [ARM] Fix several state persistence bugsKeno Fischer2016-01-122-4/+27
| | | | | | | | | | | | | | | | | | | | | | | Summary: This fixes three bugs, in all of which state is not or incorrecly reset between objects (i.e. when reusing the same pass manager to create multiple object files): 1) AttributeSection needs to be reset to nullptr, because otherwise the backend will try to emit into the old object file's attribute section causing a segmentation fault. 2) MappingSymbolCounter needs to be reset, otherwise the second object file will start where the first one left off. 3) The MCStreamer base class resets the Streamer's e_flags settings. Since EF_ARM_EABI_VER5 is set on streamer creation, we need to set it again after the MCStreamer was rest. Also rename Reset (uppser case) to EHReset to avoid confusion with reset (lower case). Reviewers: rengolin Differential Revision: http://reviews.llvm.org/D15950 llvm-svn: 257473
* CXX_FAST_TLS calling convention: performance improvement for ARM.Manman Ren2016-01-128-3/+101
| | | | | | | This is the same change on ARM as r255821 on AArch64. rdar://9001553 llvm-svn: 257424
* CXX_FAST_TLS calling convention: Add support for ARM on Darwin.Manman Ren2016-01-114-0/+16
| | | | | | rdar://9001553 llvm-svn: 257417
* RBIT Instruction only available for ARMv6t2 and above.Weiming Zhao2016-01-081-1/+1
| | | | | | | | | | | | | | | | | Summary: r255334 matches bit-reverse pattern in InstCombine and generates calls to Instrinsic::bitreverse. RBIT instruction is only available for ARMv6t2 and above. This patch has the intrinsic expanded during legalization for ARMv4 and ARMv5. Patch by Z. Zheng <zhaoshiz@codeaurora.org> Reviewers: apazos, jmolloy, weimingz Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D15932 llvm-svn: 257188
* Disable shrink-wrap for Thumb1Weiming Zhao2016-01-081-0/+5
| | | | | | | | | | | | Summary: In ARMConstantIslandPass, which runs after Shrink Wrap pass, long jumps will be fixed up as BL (tBfar) which depends on spilling LR in epilogue. However, shrink-wrap may remove the LR, which causes issues when the function returns. Reviewers: qcolombet, rengolin Subscribers: aemerson, rengolin Differential Revision: http://reviews.llvm.org/D15984 llvm-svn: 257187
* Add some testing for thumb1 and thumb2 inline asm immediate constraintsEric Christopher2016-01-081-2/+2
| | | | | | | | and fix a couple of bugs on inspection. Also fixes PR26061. llvm-svn: 257122
* ARM: support TLS accesses on Darwin platformsTim Northover2016-01-0710-8/+132
| | | | | | | | Darwin TLS accesses most closely resemble ELF's general-dynamic situation, since they have to be able to handle all possible situations. The descriptors and so on are obviously slightly different though. llvm-svn: 257039
* Extract helper function to merge MemoryOperand lists [NFC]Philip Reames2016-01-061-19/+2
| | | | | | | | | | In the discussion on http://reviews.llvm.org/D15730, Andy pointed out we had a utility function for merging MMO lists. Since it turned we actually had two copies and there's another review in progress (http://reviews.llvm.org/D15230) which needs the same, extract it into a utility function and clean up the interfaces to make it easier to use with a MachineInstBuilder. I introduced a pair here to track size and allocation together. I think we should probably move in the direction of the MachineOperandsRef helper class, but I'm leaving that for further work. I want to get the poison state introduced before I make major changes to the interface. Differential Revision: http://reviews.llvm.org/D15757 llvm-svn: 256909
* [AArch64] Add support for Samsung Exynos-M1MinSeong Kim2016-01-052-1/+9
| | | | | | | | Adds core tuning support for new Samsung Exynos-M1 core (ARMv8-A). Differential Revision: http://reviews.llvm.org/D15663 llvm-svn: 256828
* Use std::is_sorted and std::none_of instead of manual loops. NFCCraig Topper2016-01-031-6/+6
| | | | llvm-svn: 256719
* [Thumb] Fix assembler error 'cannot honor width suffix pop {lr}'Artyom Skrobov2015-12-282-50/+61
| | | | | | | | | | | | | Summary: * avoid generating POP {LR} in Thumb1 epilogues * combine MOV LR, Rx + BX LR -> BX Rx in a peephole optimization pass * combine POP {LR} + B + BX LR -> POP {PC} on v5T+ Test cases by Ana Pazos Differential Revision: http://reviews.llvm.org/D15707 llvm-svn: 256523
* Support clrex instruction on ARMv6k. Patch by Andrew Turner.Roman Divacky2015-12-281-1/+1
| | | | llvm-svn: 256505
* Remove extra forward declarations and scrub includes for all in tree ↵Craig Topper2015-12-252-3/+1
| | | | | | InstPrinters. NFC llvm-svn: 256427
* [MC, COFF] Support link /incremental conditionallyDavid Majnemer2015-12-212-7/+8
| | | | | | | | | | | | | | | | Today, we always take into account the possibility that object files produced by MC may be consumed by an incremental linker. This results in us initialing fields which vary with time (TimeDateStamp) which harms hermetic builds (e.g. verifying a self-host went well) and produces sub-optimal code because we cannot assume anything about the relative position of functions within a section (call sites can get redirected through incremental linker thunks). Let's provide an MCTargetOption which controls this behavior so that we can disable this functionality if we know a-priori that the build will not rely on /incremental. llvm-svn: 256203
* Teach ARMLoadStoreOptimizer to ignore DBG_VALUE instructions when mergingAdrian Prantl2015-12-211-1/+5
| | | | | | | | | instructions. As noted in PR24563. rdar://problem/23963293 llvm-svn: 256183
* Remove extra whitespace. NFC.Chad Rosier2015-12-211-3/+3
| | | | llvm-svn: 256173
* Fix mapping of @llvm.arm.ssat/usat intrinsics to ssat/usat instructions for ↵Weiming Zhao2015-12-201-2/+2
| | | | | | | | | | | | | | | | | Thumb2 Summary: r250697 fixed the mapping for ARM mode. We have to do the same for Thumb2 otherwise the same llvm.arm.ssat() will generate different saturating amount for ARM and Thumb. r250697: http://reviews.llvm.org/rL250697 Reviewers: rmaprath Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D15653 llvm-svn: 256115
* Revert "[ARM] Add ARMv8.2-A FP16 scalar instructions"Reid Kleckner2015-12-1612-784/+6
| | | | | | This reverts commit r255762. llvm-svn: 255806
* [ARM] Add ARMv8.2-A FP16 vector instructionsOliver Stannard2015-12-164-42/+430
| | | | | | | | | | | | | | ARMv8.2-A adds 16-bit floating point versions of all existing SIMD floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. Note that VFP without SIMD is not a valid combination for any version of ARMv8-A, but I have ensured that these instructions all depend on both FeatureNEON and FeatureFullFP16 for consistency. Differential Revision: http://reviews.llvm.org/D15039 llvm-svn: 255764
* [ARM] Add ARMv8.2-A FP16 scalar instructionsOliver Stannard2015-12-1612-6/+784
| | | | | | | | | | | | | | | | | | | | | | | | | | | ARMv8.2-A adds 16-bit floating point versions of all existing VFP floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. The assembly for these instructions uses S registers (AArch32 does not have H registers), but the instructions have ".f16" type specifiers rather than ".f32" or ".f64". The top 16 bits of each source register are ignored, and the top 16 bits of the destination register are set to zero. These instructions are mostly the same as the 32- and 64-bit versions, but they use coprocessor 9 rather than 10 and 11. Two new instructions, VMOVX and VINS, have been added to allow packing and extracting two 16-bit floats stored in the top and bottom halves of an S register. New fixup kinds have been added for the PC-relative load and store instructions, but no ELF relocations have been added as they have a range of 512 bytes. Differential Revision: http://reviews.llvm.org/D15038 llvm-svn: 255762
* Normalize MBB's successors' probabilities in several locations.Cong Hou2015-12-131-0/+1
| | | | | | | | | | | | This patch adds some missing calls to MBB::normalizeSuccProbs() in several locations where it should be called. Those places are found by checking if the sum of successors' probabilities is approximate one in MachineBlockPlacement pass with some instrumented code (not in this patch). Differential revision: http://reviews.llvm.org/D15259 llvm-svn: 255455
* ARM: only emit EABI attributes on EABI targetsSaleem Abdulrasool2015-12-131-1/+2
| | | | | | | EABI attributes should only be emitted on EABI targets. This prevents the emission of the optimization goals EABI attribute on Windows ARM. llvm-svn: 255448
* Revert r248483, r242546, r242545, and r242409 - absdiff intrinsicsHal Finkel2015-12-112-22/+8
| | | | | | | | | | | | | | | | | | | | After much discussion, ending here: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20151123/315620.html it has been decided that, instead of having the vectorizer directly generate special absdiff and horizontal-add intrinsics, we'll recognize the relevant reduction patterns during CodeGen. Accordingly, these intrinsics are not needed (the operations they represent can be pattern matched, as is already done in some backends). Thus, we're backing these out in favor of the current development work. r248483 - Codegen: Fix llvm.*absdiff semantic. r242546 - [ARM] Use [SU]ABSDIFF nodes instead of intrinsics for VABD/VABA r242545 - [AArch64] Use [SU]ABSDIFF nodes instead of intrinsics for ABD/ABA r242409 - [Codegen] Add intrinsics 'absdiff' and corresponding SDNodes for absolute difference operation llvm-svn: 255387
* CodeGen: Redo analyzePhysRegs() and computeRegisterLiveness()Matthias Braun2015-12-111-13/+2
| | | | | | | | | | | | | | | | | | | | computeRegisterLiveness() was broken in that it reported dead for a register even if a subregister was alive. I assume this was because the results of analayzePhysRegs() are hard to understand with respect to subregisters. This commit: Changes the results of analyzePhysRegs (=struct PhysRegInfo) to be clearly understandable, also renames the fields to avoid silent breakage of third-party code (and improve the grammar). Fix all (two) users of computeRegisterLiveness() in llvm: By reenabling it and removing workarounds for the bug. This fixes http://llvm.org/PR24535 and http://llvm.org/PR25033 Differential Revision: http://reviews.llvm.org/D15320 llvm-svn: 255362
* ARM: don't use a deleted node as the BaseReg in complex pattern.Tim Northover2015-12-091-1/+4
| | | | | | | | | | We mutated the DAG, which invalidated the node we were trying to use as a base register. Sometimes we got away with it, but other times the node really did get deleted before it was finished with. Should fix PR25733 llvm-svn: 255120
OpenPOWER on IntegriCloud