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* Move kill flags when the same register occurs more than once in a sequence.Jakob Stoklund Olesen2009-12-231-1/+22
| | | | llvm-svn: 92058
* Handle undef operands properly.Jakob Stoklund Olesen2009-12-231-4/+8
| | | | llvm-svn: 92054
* Make insert position available to MergeOpsUpdate.Jakob Stoklund Olesen2009-12-231-24/+25
| | | | | | | Rearrange arguments. No functional changes llvm-svn: 92053
* Perform kill flag calculations in new method. No functional changes.Jakob Stoklund Olesen2009-12-231-12/+15
| | | | llvm-svn: 92052
* Move repeated code to a new method. No functional change.Jakob Stoklund Olesen2009-12-231-17/+47
| | | | llvm-svn: 92051
* Add a SPR register class to the ARM target.Jakob Stoklund Olesen2009-12-222-1/+14
| | | | | | Certain Thumb instructions require only SP (e.g. tSTRspi). llvm-svn: 91944
* Use proper move instructions. Make the verifier happy.Jakob Stoklund Olesen2009-12-221-1/+1
| | | | llvm-svn: 91914
* Add more plumbing. This time in the LowerArguments and "get" functions whichBill Wendling2009-12-221-1/+2
| | | | | | | | return partial registers. This affected the back-end lowering code some. Also patch up some places I missed before in the "get" functions. llvm-svn: 91880
* Delete the instruction just before the function terminates for consistency sake.Evan Cheng2009-12-211-2/+3
| | | | llvm-svn: 91836
* Fix a bunch of little errors that Clang complains about when its being pedanticDouglas Gregor2009-12-191-1/+1
| | | | llvm-svn: 91764
* Fix libstdc++ build on ARM linux and part of PR5770.Rafael Espindola2009-12-181-0/+3
| | | | | | | | | | | | | | MI was not being used but it was also not being deleted, so it was kept in the garbage list. The memory itself was freed once the function code gen was done. Once in a while the codegen of another function would create an instruction on the same address. Adding it to the garbage group would work once, but when another pointer was added it would cause an assert as "Cache" was about to be pushed to Ts. For a patch that make us detect problems like this earlier, take a look at http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20091214/092758.html With that patch we assert as soon and the new instruction is added to the garbage set. llvm-svn: 91691
* Handle ARM inline asm "w" constraints with 64-bit ("d") registers.Bob Wilson2009-12-181-2/+2
| | | | | | | | The change in SelectionDAGBuilder is needed to allow using bitcasts to convert between f64 (the default type for ARM "d" registers) and 64-bit Neon vector types. Radar 7457110. llvm-svn: 91649
* Renamed "tCMNZ" to "tCMNz" to be consistent with other similar namings.Johnny Chen2009-12-161-1/+1
| | | | llvm-svn: 91571
* Silence a clang warning about the deprecated (but perfectly reasonable inJohn McCall2009-12-161-2/+2
| | | | | | context) increment-of-bool idiom. llvm-svn: 91564
* Mark STREX* as earlyclobber for the success result register.Jim Grosbach2009-12-162-2/+2
| | | | llvm-svn: 91555
* Add encoding bits for some Thumb instructions. Plus explicitly set the top twoJohnny Chen2009-12-163-10/+18
| | | | | | bytes of Inst to 0x0000 for the benefit of the Thumb decoder. llvm-svn: 91496
* Every anonymous namespace is different. Caught by clang++.John McCall2009-12-161-4/+0
| | | | llvm-svn: 91481
* Change indirect-globals to use a dedicated allocIndirectGV. This lets usJeffrey Yasskin2009-12-151-11/+5
| | | | | | | | | remove start/finishGVStub and the BufferState helper class from the MachineCodeEmitter interface. It has the side-effect of not setting the indirect global writable and then executable on ARM, but that shouldn't be necessary. llvm-svn: 91464
* Added encoding bits for the Thumb ISA. Initial checkin.Johnny Chen2009-12-153-348/+1219
| | | | llvm-svn: 91434
* nand atomic requires opposite operand orderingJim Grosbach2009-12-151-3/+9
| | | | llvm-svn: 91371
* Add encoding bits "let Inst{11-4} = 0b00000000;" to BR_JTr to disambiguateJohnny Chen2009-12-141-0/+1
| | | | | | between BR_JTr and STREXD. llvm-svn: 91339
* v6 sync insn copy/paste errorJim Grosbach2009-12-141-1/+1
| | | | llvm-svn: 91333
* Add ARMv6 memory and sync barrier instructionsJim Grosbach2009-12-143-14/+45
| | | | llvm-svn: 91329
* Fixed encoding bits typo of ldrexd/strexd.Johnny Chen2009-12-141-2/+2
| | | | llvm-svn: 91327
* Thumb2 atomic operationsJim Grosbach2009-12-141-44/+83
| | | | llvm-svn: 91321
* correct selection requirements for thumb2 vs. arm versions of the barrier ↵Jim Grosbach2009-12-142-4/+6
| | | | | | intrinsics llvm-svn: 91313
* add Thumb2 atomic and memory barrier instruction definitionsJim Grosbach2009-12-141-0/+60
| | | | llvm-svn: 91310
* whitespaceJim Grosbach2009-12-141-1/+0
| | | | llvm-svn: 91307
* ARM memory barrier instructions are not predicableJim Grosbach2009-12-142-3/+20
| | | | llvm-svn: 91305
* add ldrexd/strexd instructionsJim Grosbach2009-12-141-2/+11
| | | | llvm-svn: 91284
* atomic binary operations up to 32-bits wide.Jim Grosbach2009-12-141-5/+63
| | | | llvm-svn: 91260
* Framework for atomic binary operations. The emitter for the pseudo instructionsJim Grosbach2009-12-123-19/+150
| | | | | | | just issues an error for the moment. The front end won't yet generate these intrinsics for ARM, so this is behind the scenes until complete. llvm-svn: 91200
* memory barrier instructions by definition have side effects. This prevents ↵Jim Grosbach2009-12-111-1/+1
| | | | | | the post-RA scheduler from moving them around. llvm-svn: 91150
* Store Register Exclusive should leave the source register Inst{3-0} unspecified.Johnny Chen2009-12-111-1/+1
| | | | llvm-svn: 91143
* Update properties.Jim Grosbach2009-12-111-2/+2
| | | | llvm-svn: 91140
* Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in ↵Jim Grosbach2009-12-115-0/+152
| | | | | | progress. llvm-svn: 91090
* Add instruction encoding for DMB/DSBJim Grosbach2009-12-101-3/+11
| | | | llvm-svn: 91053
* Add memory barrier intrinsic support for ARM. Moving towards adding the ↵Jim Grosbach2009-12-103-1/+49
| | | | | | atomic operations intrinsics. llvm-svn: 91003
* - Support inline asm 'w' constraint for 128-bit vector types.Evan Cheng2009-12-082-0/+6
| | | | | | - Also support the 'q' NEON registers asm code. llvm-svn: 90894
* Dynamic stack realignment use of sp register as source/dest registerAnton Korobeynikov2009-12-061-4/+27
| | | | | | | | | | in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode. Emit the following code instead: mov r4, sp bic r4, r4, #15 mov sp, r4 llvm-svn: 90724
* Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor ofDan Gohman2009-12-057-74/+0
| | | | | | | MachineBasicBlock::canFallThrough(), which is target-independent and more thorough. llvm-svn: 90634
* remove out of date FIXME.Jim Grosbach2009-12-031-1/+0
| | | | llvm-svn: 90490
* fix a build problem with VC++, PR5664, patch by Alp Toker!Chris Lattner2009-12-031-2/+4
| | | | llvm-svn: 90419
* Recognize canonical forms of vector shuffles where the same vector is used forBob Wilson2009-12-031-1/+87
| | | | | | | | both source operands. In the canonical form, the 2nd operand is changed to an undef and the shuffle mask is adjusted to only reference elements from the 1st operand. Radar 7434842. llvm-svn: 90417
* improve portability to avoid conflicting with std::next in c++'0x.Chris Lattner2009-12-037-19/+19
| | | | | | Patch by Howard Hinnant! llvm-svn: 90365
* Factor the stack alignment calculations out into a target independent pass.Jim Grosbach2009-12-023-65/+3
| | | | | | No functionality change. llvm-svn: 90336
* Thumb1 exception handling setjmpJim Grosbach2009-12-013-0/+42
| | | | llvm-svn: 90246
* For VLDM/VSTM (Advanced SIMD), set encoding bits Inst{11-8} to 0b1011.Johnny Chen2009-12-011-2/+2
| | | | llvm-svn: 90243
* For VMOV (immediate), make some of the encoding bits (cmode and op) unspecified.Johnny Chen2009-12-011-4/+4
| | | | | | | | For VMOVv*i[16,32], op bit is don't care, and some cmode bits vary depending on the immediate values. Ref: Table A7-15 Modified immediate values for Advanced SIMD instructions. llvm-svn: 90173
* Remove isProfitableToDuplicateIndirectBranch target hook. It is profitableBob Wilson2009-11-304-15/+0
| | | | | | | | | for all the processors where I have tried it, and even when it might not help performance, the cost is quite low. The opportunities for duplicating indirect branches are limited by other factors so code size does not change much due to tail duplicating indirect branches aggressively. llvm-svn: 90144
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