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* ARM unified syntax is not specific to ELF; use it for Darwin, too.Bob Wilson2009-06-181-1/+1
| | | | llvm-svn: 73665
* Fix asm string from MOVi16Anton Korobeynikov2009-06-171-1/+1
| | | | llvm-svn: 73661
* Thumb2 instructions are enabled only in unified assembler mode.Anton Korobeynikov2009-06-171-0/+4
| | | | | | | Emit switch directive for it. I have no idea whether this is requirement for Darwin or not. llvm-svn: 73660
* Initial support for some Thumb2 instructions.Anton Korobeynikov2009-06-174-3/+262
| | | | | | Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc. llvm-svn: 73622
* Introduce new headers whose inclusion forces linking andDouglas Gregor2009-06-162-0/+11
| | | | | | | | | initialization of all targets (InitializeAllTargets.h) or assembler printers (InitializeAllAsmPrinters.h). This is a step toward the elimination of relinked object files, so that we can build normal archives. llvm-svn: 73543
* Address review comments: add 3 ARM calling conventions.Anton Korobeynikov2009-06-163-34/+35
| | | | | | | Dispatch C calling conv. to one of these conventions based on target triple and subtarget features. llvm-svn: 73530
* GNU as refuses to assemble "pop {}" instruction. Do not emit suchAnton Korobeynikov2009-06-161-2/+6
| | | | | | | (this is the case when we have thumb vararg function with single callee-saved register, which is handled separately). llvm-svn: 73529
* On Darwin, frame pointer r7 is never available.Evan Cheng2009-06-151-2/+2
| | | | llvm-svn: 73434
* Rename methods for the sake of consistency.Anton Korobeynikov2009-06-152-8/+8
| | | | llvm-svn: 73428
* Typo.Evan Cheng2009-06-151-1/+1
| | | | llvm-svn: 73422
* Do not form ldrd / strd if the two dests / srcs are the same. Code clean up.Evan Cheng2009-06-151-59/+73
| | | | llvm-svn: 73413
* Silence a warning.Evan Cheng2009-06-151-1/+1
| | | | llvm-svn: 73406
* Part 1.Evan Cheng2009-06-155-23/+533
| | | | | | | | | | | | | | | | | | | | | - Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. llvm-svn: 73381
* Add a ARM specific pre-allocation pass that re-schedule loads / stores fromEvan Cheng2009-06-134-27/+333
| | | | | | | | | | | consecutive addresses togther. This makes it easier for the post-allocation pass to form ldm / stm. This is step 1. We are still missing a lot of ldm / stm opportunities because of register allocation are not done in the desired order. More enhancements coming. llvm-svn: 73291
* Mark some pattern-less instructions as neverHasSideEffects.Evan Cheng2009-06-123-1/+9
| | | | llvm-svn: 73252
* TypoAnton Korobeynikov2009-06-081-1/+1
| | | | llvm-svn: 73098
* Revert hunk commited by accidentAnton Korobeynikov2009-06-081-7/+2
| | | | llvm-svn: 73097
* The attached patches implement most of the ARM AAPCS-VFP hard floatAnton Korobeynikov2009-06-085-12/+85
| | | | | | | | | ABI. The missing piece is support for putting "homogeneous aggregates" into registers. Patch by Sandeep Patel! llvm-svn: 73095
* Separate V6 from V6T2 since the latter has some extra nice instructionsAnton Korobeynikov2009-06-082-3/+8
| | | | llvm-svn: 73085
* Add helper for checking of Thumb1 modeAnton Korobeynikov2009-06-081-0/+1
| | | | llvm-svn: 73080
* Add explicit keywords.Dan Gohman2009-06-051-1/+1
| | | | llvm-svn: 72969
* Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order ↵Evan Cheng2009-06-052-10/+10
| | | | | | change no longer make sense after the coalescing changes we have made since then. llvm-svn: 72955
* When merging multiple load / store instructions. Use the DebugLoc of the ↵Evan Cheng2009-06-051-11/+16
| | | | | | first one. llvm-svn: 72952
* Code clean up: return vector by reference rather than by value. No ↵Evan Cheng2009-06-051-21/+21
| | | | | | functionality changes. llvm-svn: 72950
* Remove some unnecessary #includes.Dan Gohman2009-06-051-1/+0
| | | | llvm-svn: 72948
* Re-apply 72756 with fixes. One of those was introduced by we changed ↵Evan Cheng2009-06-041-1/+8
| | | | | | MachineInstrBuilder::addReg() interface. llvm-svn: 72826
* Temporarily revert 72756 for now.Evan Cheng2009-06-031-7/+0
| | | | llvm-svn: 72757
* Fold preceding / trailing base inc / dec into the single load / store as well.Evan Cheng2009-06-031-2/+9
| | | | llvm-svn: 72756
* Implement review feedback. Make thumb2 'normal' subtarget featureAnton Korobeynikov2009-06-012-13/+12
| | | | llvm-svn: 72698
* Fix new CodeEmitter stuff to follow LLVM codying style. Patch by Aaron GrayBruno Cardoso Lopes2009-06-012-104/+103
| | | | llvm-svn: 72697
* Do not emit "generic" CPU string. This fixes PR4291.Anton Korobeynikov2009-06-011-1/+3
| | | | llvm-svn: 72696
* First patch in the direction of splitting MachineCodeEmitter in two subclasses:Bruno Cardoso Lopes2009-05-306-80/+189
| | | | | | JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray llvm-svn: 72631
* Untabification.Bill Wendling2009-05-301-1/+1
| | | | llvm-svn: 72604
* Add placeholder for thumb2 stuffAnton Korobeynikov2009-05-295-20/+53
| | | | llvm-svn: 72593
* fix typoChris Lattner2009-05-251-1/+1
| | | | llvm-svn: 72395
* Add ARMv7 architecture, Cortex processors and different FPU modes handling.Anton Korobeynikov2009-05-233-13/+28
| | | | llvm-svn: 72337
* Emit ARM Build AttributesAnton Korobeynikov2009-05-232-0/+91
| | | | llvm-svn: 72336
* Propagate CPU string out of SubtargetFeaturesAnton Korobeynikov2009-05-232-5/+10
| | | | llvm-svn: 72335
* Only 64-bit targets support TImode libcalls. Disable the TImode shift libcallsBob Wilson2009-05-221-0/+5
| | | | | | for ARM. This fixes rdar://6908807. llvm-svn: 72269
* Minor formatting fixes.Bob Wilson2009-05-201-2/+2
| | | | llvm-svn: 72172
* Fix pr4227: Handle large immediate values in inline assembly.Bob Wilson2009-05-191-1/+1
| | | | llvm-svn: 72138
* Follow up on new support for memory operands in ARM inline assembly.Bob Wilson2009-05-191-0/+4
| | | | | | This fixes pr4233. llvm-svn: 72115
* Fix pr4058 and pr4059. Do not split i64 or double arguments between r3 andBob Wilson2009-05-191-1/+4
| | | | | | the stack. Patch by Sandeep Patel. llvm-svn: 72106
* Fix pr4091: Add support for "m" constraint in ARM inline assembly.Bob Wilson2009-05-192-0/+34
| | | | llvm-svn: 72105
* Fix pr4202: Disable CodePlacementOpt for ARM. The ARMConstantIslandPass hasBob Wilson2009-05-181-1/+4
| | | | | | | | | to run last because it needs to know the exact size and position of every basic block. Currently CodePlacementOpt is set up to run last. It might be worthwhile to investigate reordering these passes, but for now, let's just make it work. llvm-svn: 72037
* Update the names of the exception handling sjlj instrinsics toJim Grosbach2009-05-144-14/+16
| | | | | | | | | llvm.eh.sjlj.* for better clarity as to their purpose and scope. Add a description of llvm.eh.sjlj.setjmp to ExceptionHandling.html. (llvm.eh.sjlj.longjmp documentation coming when that implementation is added). llvm-svn: 71758
* Spelling correction s/builting/builtin/ and remove trailing whitespace in a ↵Jim Grosbach2009-05-131-10/+10
| | | | | | few places llvm-svn: 71735
* Run code placement optimization for targets that want it (arm and x86 for now).Evan Cheng2009-05-131-0/+1
| | | | llvm-svn: 71726
* Change MachineInstrBuilder::addReg() to take a flag instead of a list ofBill Wendling2009-05-133-37/+38
| | | | | | | | | | | | booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). llvm-svn: 71722
* Add support for GCC compatible builtin setjmp and longjmp intrinsics. This isJim Grosbach2009-05-124-4/+52
| | | | | | | a supporting preliminary patch for GCC-compatible SjLJ exception handling. Note that these intrinsics are not designed to be invoked directly by the user, but rather used by the front-end as target hooks for exception handling. llvm-svn: 71610
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