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* Rename ARM "lane_cst" operands to "nohash_imm" since they are used forBob Wilson2009-08-215-18/+20
| | | | | | | several things other than Neon vector lane numbers. For inline assembly operands with a "c" print code, check that they really are immediates. llvm-svn: 79676
* Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations,Bob Wilson2009-08-212-9/+74
| | | | | | now using shuffles instead of intrinsics. llvm-svn: 79673
* Fix some typos and use type-based isel for VZIP/VUZP/VTRNAnton Korobeynikov2009-08-214-56/+56
| | | | llvm-svn: 79625
* Add lowering of ARM 4-element shuffles to multiple instructios via ↵Anton Korobeynikov2009-08-213-9/+6720
| | | | | | perfectshuffle-generated table. llvm-svn: 79624
* Add nodes & dummy matchers for some v{zip,uzp,trn} instructionsAnton Korobeynikov2009-08-213-0/+51
| | | | llvm-svn: 79622
* Expand EXTRACT_SUBVECTORAnton Korobeynikov2009-08-211-0/+1
| | | | llvm-svn: 79621
* Provide vext.{16,32}Anton Korobeynikov2009-08-212-13/+23
| | | | llvm-svn: 79620
* Use masks not nodes for vector shuffle predicates. Provide set of 'legal' ↵Anton Korobeynikov2009-08-212-15/+34
| | | | | | masks, so legalizer won't infinite cycle llvm-svn: 79619
* Remove Neon intrinsics for VZIP, VUZP, and VTRN. We will represent these asBob Wilson2009-08-211-57/+0
| | | | | | | vector shuffles. Temporarily remove the tests for these operations until the new implementation is working. llvm-svn: 79579
* Fix an obvious copy-n-paste bug.Evan Cheng2009-08-201-1/+1
| | | | llvm-svn: 79535
* Update Cortex-A8 instruction itineraries for integer instructions.David Goodwin2009-08-196-365/+650
| | | | llvm-svn: 79436
* Add support for Neon VEXT (vector extract) shuffles.Bob Wilson2009-08-193-1/+69
| | | | | | | | This is derived from a patch by Anton Korzh. I modified it to recognize the VEXT shuffles during legalization and lower them to a target-specific DAG node. llvm-svn: 79428
* eliminate AsmPrinter::SwitchToSection and just have clientsChris Lattner2009-08-191-7/+8
| | | | | | talk to the MCStreamer directly instead. llvm-svn: 79405
* Simplify RegScavenger::FindUnusedReg.Jakob Stoklund Olesen2009-08-182-11/+3
| | | | | | | | | - Drop the Candidates argument and fix all callers. Now that RegScavenger tracks available registers accurately, there is no need to restict the search. - Make sure that no aliases of the found register are in use. This was a potential bug. llvm-svn: 79369
* Fix revsh pattern.Evan Cheng2009-08-182-2/+2
| | | | llvm-svn: 79318
* Fix use after free in Thumb2SizeReduction (PR4707). A MachineInstr was used ↵Benjamin Kramer2009-08-161-1/+4
| | | | | | after erasure. llvm-svn: 79189
* Reapply r79127. It was fixed by d0k.Bill Wendling2009-08-152-0/+28
| | | | llvm-svn: 79136
* Revert r79127. It was causing compilation errors.Bill Wendling2009-08-152-28/+0
| | | | llvm-svn: 79135
* Change allowsUnalignedMemoryAccesses to take type argument since some targetsEvan Cheng2009-08-152-0/+28
| | | | | | | | | | support unaligned mem access only for certain types. (Should it be size instead?) ARM v7 supports unaligned access for i16 and i32, some v6 variants support it as well. llvm-svn: 79127
* Turn on if-conversion for thumb2.Evan Cheng2009-08-159-51/+57
| | | | llvm-svn: 79084
* Do not use frame register to reference fixed stack objects if the function ↵Evan Cheng2009-08-152-13/+14
| | | | | | is frameless. llvm-svn: 79067
* Leaf functions which do not save CSRs can be frameless even with ↵Evan Cheng2009-08-142-1/+10
| | | | | | -disable-fp-elim. llvm-svn: 79039
* Allow targets to specify their choice of calling conventions perAnton Korobeynikov2009-08-141-0/+9
| | | | | | | | | | libcall. Take advantage of this in the ARM backend to rectify broken choice of CC when hard float is in effect. PIC16 may want to see if it could be of use in MakePIC16Libcall, which works unchanged. Patch by Sandeep! llvm-svn: 79033
* Add Thumb2 lsr hooks.Evan Cheng2009-08-142-36/+106
| | | | llvm-svn: 79032
* 80 col violation.Evan Cheng2009-08-141-1/+2
| | | | llvm-svn: 79026
* Indentation.Evan Cheng2009-08-141-1/+1
| | | | llvm-svn: 79022
* Also shrink immediate branches; also more assembler workarounds.Evan Cheng2009-08-142-11/+59
| | | | llvm-svn: 79014
* Now that all the legal Neon shuffles (or at least the ones that have beenBob Wilson2009-08-141-1/+1
| | | | | | | implemented so far) are recognized during legalization, it is easy to fall back to the default expansion for other shuffles. llvm-svn: 78995
* Create a new ARM-specific DAG node, VDUP, to represent a splat from aBob Wilson2009-08-143-26/+19
| | | | | | | scalar_to_vector. Generate these VDUP nodes during legalization instead of trying to recognize the pattern during selection. llvm-svn: 78994
* During legalization, change Neon vdup_lane operations from shuffles toBob Wilson2009-08-144-61/+33
| | | | | | | | target-specific VDUPLANE nodes. This allows the subreg handling for the quad-register version to be done easily with Pats in the .td file, instead of with custom code in ARMISelDAGToDAG.cpp. llvm-svn: 78993
* Shrink ADR and LDR from constantpool late during constantpool island pass.Evan Cheng2009-08-144-16/+79
| | | | llvm-svn: 78970
* New entry.Evan Cheng2009-08-141-0/+3
| | | | llvm-svn: 78968
* Push LLVMContexts through the IntegerType APIs.Owen Anderson2009-08-139-16/+28
| | | | llvm-svn: 78948
* Revert 78892 and 78895, these break generating working executables onDaniel Dunbar2009-08-133-4/+3
| | | | | | | | | | | | | | | | | | | | | x86_64-apple-darwin10. --- Reverse-merging r78895 into '.': U test/CodeGen/PowerPC/2008-12-12-EH.ll U lib/Target/DarwinTargetAsmInfo.cpp --- Reverse-merging r78892 into '.': U include/llvm/Target/DarwinTargetAsmInfo.h U lib/Target/X86/X86TargetAsmInfo.cpp U lib/Target/X86/X86TargetAsmInfo.h U lib/Target/ARM/ARMTargetAsmInfo.h U lib/Target/ARM/ARMTargetMachine.cpp U lib/Target/ARM/ARMTargetAsmInfo.cpp U lib/Target/PowerPC/PPCTargetAsmInfo.cpp U lib/Target/PowerPC/PPCTargetAsmInfo.h U lib/Target/PowerPC/PPCTargetMachine.cpp G lib/Target/DarwinTargetAsmInfo.cpp llvm-svn: 78919
* Add missing defs of R2 and D1.Jim Grosbach2009-08-132-4/+4
| | | | llvm-svn: 78918
* Finalize itineraries for cortex-a8 integer multiplyDavid Goodwin2009-08-136-55/+65
| | | | llvm-svn: 78908
* Remove unnecessary newlineJim Grosbach2009-08-132-2/+2
| | | | llvm-svn: 78905
* Correct comment wordingJim Grosbach2009-08-132-2/+2
| | | | llvm-svn: 78904
* tPOP_RET now has predicate operands.Evan Cheng2009-08-131-2/+2
| | | | llvm-svn: 78898
* Add a fixme message about canonicalizing floating-point vector types.Bob Wilson2009-08-131-0/+2
| | | | llvm-svn: 78897
* Revert r78852 for now. I want to do this differently, but I don't have timeBob Wilson2009-08-133-18/+23
| | | | | | to fix it tonight. llvm-svn: 78896
* It's ok to spill a tGPR register as long as it's still allocated a low register.Evan Cheng2009-08-131-6/+14
| | | | llvm-svn: 78893
* fix a minor fixme. When building with SL and later tools, the ".eh" symbolsChris Lattner2009-08-133-3/+4
| | | | | | don't need to be exported from the .o files. llvm-svn: 78892
* Change MCSectionELF to represent a section semantically instead ofBruno Cardoso Lopes2009-08-131-4/+5
| | | | | | | syntactically as a string, very similiar to what Chris did with MachO. The parsing support and validation is not introduced yet. llvm-svn: 78890
* Add a comment to describe why vector shuffles are legalized to custom DAG nodes.Bob Wilson2009-08-131-0/+4
| | | | llvm-svn: 78884
* Use cast<> instead of dyn_cast<> in places where the type is known.Bob Wilson2009-08-131-5/+3
| | | | llvm-svn: 78881
* Various AsmWriter output cleanups. Use WriteAsOperand instead ofDan Gohman2009-08-131-13/+4
| | | | | | PrintUnmangledNameSafely. llvm-svn: 78878
* Recognize Neon VDUP shuffles during legalization instead of selection.Bob Wilson2009-08-123-23/+18
| | | | llvm-svn: 78852
* Recognize Neon VREV shuffles during legalization instead of selection.Bob Wilson2009-08-123-32/+34
| | | | llvm-svn: 78850
* This void is implicit in C++.Dan Gohman2009-08-121-1/+1
| | | | llvm-svn: 78848
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