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* Have ARM ELF use correct reloc for "b" instr.Jan Wen Voung2012-06-191-5/+3
| | | | | | | The condition code didn't actually matter for arm "b" instructions, unlike "bl". It should just use the R_ARM_JUMP24 reloc. llvm-svn: 158722
* Move the support for using .init_array from ARM to the genericRafael Espindola2012-06-192-45/+2
| | | | | | | | | | TargetLoweringObjectFileELF. Use this to support it on X86. Unlike ARM, on X86 it is not easy to find out if .init_array should be used or not, so the decision is made via TargetOptions and defaults to off. Add a command line option to llc that enables it. llvm-svn: 158692
* ARM: use NOEN loads and stores if possible when handling struct byval.Manman Ren2012-06-181-8/+42
| | | | | | | | This change is to be enabled in clang. rdar://9877866 llvm-svn: 158684
* ARM: Define generic HINT instruction.Jim Grosbach2012-06-184-50/+46
| | | | | | | | | | | The NOP, WFE, WFI, SEV and YIELD instructions are all hints w/ a different immediate value in bits [7,0]. Define a generic HINT instruction and refactor NOP, WFI, WFI, SEV and YIELD to be assembly aliases of that. rdar://11600518 llvm-svn: 158674
* This change handles a another case for generating the bic instruction Joel Jones2012-06-181-0/+31
| | | | | | | | | | | when a compile time constant is known. This occurs when implicitly zero extending function arguments from 16 bits to 32 bits. The 8 bit case doesn't need to be handled, as the 8 bit constants are encoded directly, thereby not needing a separate load instruction to form the constant into a register. <rdar://problem/11481151> llvm-svn: 158659
* Fix the encoding of the armv7m (MClass) for MSR registers other than aspr,Kevin Enderby2012-06-152-21/+31
| | | | | | iaspr, espr and xpsr which also needed to have 0b10 in their mask encoding bits. llvm-svn: 158560
* ARM: optimization for sub+abs.Manman Ren2012-06-151-11/+6
| | | | | | | | | | | | | | This patch will optimize abs(x-y) FROM sub, movs, rsbmi TO subs, rsbmi For abs, we will use cmp instead of movs. This is necessary because we already have an existing peephole pass which optimizes away cmp following sub. rdar: 11633193 llvm-svn: 158551
* Preserve <undef> flags in ARMExpandPseudo.Jakob Stoklund Olesen2012-06-151-5/+6
| | | | | | This probably mostly shows up in bugpoint-generated code. llvm-svn: 158527
* Replace assertion failure for badly formatted CPS instrution with error message.Richard Barton2012-06-141-1/+2
| | | | llvm-svn: 158445
* Cleanup whitespace.Jush Lu2012-06-141-13/+12
| | | | llvm-svn: 158443
* [arm-fast-isel] Add support for -arm-long-calls.Chad Rosier2012-06-121-41/+57
| | | | | | Patch by Jush Lu <jush.msn@gmail.com>. llvm-svn: 158368
* Re-enable the CMN instruction.Bill Wendling2012-06-115-69/+144
| | | | | | | | | We turned off the CMN instruction because it had semantics which we weren't getting correct. If we are comparing with an immediate, then it's okay to use the CMN instruction. <rdar://problem/7569620> llvm-svn: 158302
* Continue factoring computeOperandLatency. Use it for ARM hasHighOperandLatency.Andrew Trick2012-06-071-1/+2
| | | | llvm-svn: 158164
* ARM getOperandLatency rewrite.Andrew Trick2012-06-071-85/+112
| | | | | | Match expectations of the new latency API. Cleanup and make the logic consistent. llvm-svn: 158163
* ARM getOperandLatency should return -1 for unknown, consistent with APIAndrew Trick2012-06-071-1/+4
| | | | llvm-svn: 158162
* Fix ARM getInstrLatency logic to work with the current API.Andrew Trick2012-06-071-13/+19
| | | | llvm-svn: 158161
* Remove unused private fields found by clang's new -Wunused-private-field.Benjamin Kramer2012-06-061-2/+0
| | | | | | | | There are some that I didn't remove this round because they looked like obvious stubs. There are dead variables in gtest too, they should be fixed upstream. llvm-svn: 158090
* Correct decoder for T1 conditional B encodingRichard Barton2012-06-061-2/+2
| | | | llvm-svn: 158055
* misched: API for minimum vs. expected latency.Andrew Trick2012-06-052-10/+14
| | | | | | | Minimum latency determines per-cycle scheduling groups. Expected latency determines critical path and cost. llvm-svn: 158021
* ARM itinerary properties.Andrew Trick2012-06-053-22/+10
| | | | llvm-svn: 157980
* misched: Added MultiIssueItineraries.Andrew Trick2012-06-051-3/+4
| | | | | | | | This allows a subtarget to explicitly specify the issue width and other properties without providing pipeline stage details for every instruction. llvm-svn: 157979
* Revert commit r157966Joel Jones2012-06-051-24/+0
| | | | llvm-svn: 157972
* This change handles a another case for generating the bic instruction Joel Jones2012-06-041-0/+24
| | | | | | | | | when a compile time constant is known. This occurs when implicitly zero extending function arguments from 16 bits to 32 bits. <rdar://problem/11481151> llvm-svn: 157966
* Fix typos found by http://github.com/lyda/misspell-checkBenjamin Kramer2012-06-023-7/+7
| | | | llvm-svn: 157885
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-011-4/+2
| | | | | | | | | | | | | No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). llvm-svn: 157854
* [arm-fast-isel] Fix handling of the frameaddress intrinsic. If depth is 0Chad Rosier2012-06-011-1/+1
| | | | | | then DestReg is undefined. llvm-svn: 157840
* ARM: properly handle alignment for struct byval.Manman Ren2012-06-013-250/+275
| | | | | | | | | Factor out the expansion code into a function. This change is to be enabled in clang. rdar://9877866 llvm-svn: 157830
* ARM: support struct byval in llvmManman Ren2012-06-013-15/+279
| | | | | | | | | | We handle struct byval by inserting a pseudo op, which will be expanded to a loop at ExpandISelPseudos. A separate patch for clang will be submitted to enable struct byval. rdar://9877866 llvm-svn: 157793
* Avoid depending on list orders and register numbering.Jakob Stoklund Olesen2012-05-301-6/+9
| | | | | | This code is covered by test/CodeGen/ARM/arm-modifier.ll. llvm-svn: 157720
* [arm-fast-isel] Add support for the llvm.frameaddress() intrinsic.Chad Rosier2012-05-301-0/+36
| | | | | | Patch by Jush Lu <jush.msn@gmail.com>. llvm-svn: 157696
* Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCallJustin Holewinski2012-05-253-19/+21
| | | | | | | | | | to pass around a struct instead of a large set of individual values. This cleans up the interface and allows more information to be added to the struct for future targets without requiring changes to each and every target. NV_CONTRIB llvm-svn: 157479
* Make some opcode tables static and const. Allows code to avoid making copies ↵Craig Topper2012-05-241-173/+219
| | | | | | to pass the tables around. llvm-svn: 157373
* Mark a static array as const.Craig Topper2012-05-241-1/+1
| | | | llvm-svn: 157368
* Mark a static table as const. Shrink opcode size in static tables to ↵Craig Topper2012-05-241-14/+9
| | | | | | uint16_t. Simplify loop iterating over one of those tables. No functional change intended. llvm-svn: 157367
* [arm-fast-isel] Add support for non-global callee.Chad Rosier2012-05-231-7/+17
| | | | | | Patch by Jush Lu <jush.msn@gmail.com>. llvm-svn: 157336
* ARMDisassembler.cpp: Fix utf8 char in comments.NAKAMURA Takumi2012-05-221-3/+3
| | | | llvm-svn: 157292
* ARM: .end_data_region mismatch in Thumb2.Jim Grosbach2012-05-211-2/+5
| | | | | | | | | | 32-bit offset jump tables just use real branch instructions and so aren't marked as data regions. We were still emitting the .end_data_region marker though, which assert()ed. rdar://11499158 llvm-svn: 157221
* Thumb2: RSB source register should be rGRP not GPRnopc.Jim Grosbach2012-05-211-4/+4
| | | | | | t2RSB defined the operand correctly, but tRSBS didn't. llvm-svn: 157200
* Use the right register class for LDRrs.Jakob Stoklund Olesen2012-05-201-1/+1
| | | | llvm-svn: 157152
* Transfer memory operands to the right instruction.Jakob Stoklund Olesen2012-05-201-1/+1
| | | | | | They need to go on the PICLDR as the verifier points out. llvm-svn: 157151
* Refactor data-in-code annotations.Jim Grosbach2012-05-183-22/+40
| | | | | | | | | | | | | | | | | | | | | | Use a dedicated MachO load command to annotate data-in-code regions. This is the same format the linker produces for final executable images, allowing consistency of representation and use of introspection tools for both object and executable files. Data-in-code regions are annotated via ".data_region"/".end_data_region" directive pairs, with an optional region type. data_region_directive := ".data_region" { region_type } region_type := "jt8" | "jt16" | "jt32" | "jta32" end_data_region_directive := ".end_data_region" The previous handling of ARM-style "$d.*" labels was broken and has been removed. Specifically, it didn't handle ARM vs. Thumb mode when marking the end of the section. rdar://11459456 llvm-svn: 157062
* Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missingKevin Enderby2012-05-173-11/+54
| | | | | | | | | | the 0b10 mask encoding bits. Make MSR APSR writes without a _<bits> qualifier an alias for MSR APSR_nzcvq even though ARM as deprecated it use. Also add support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions. Some FIXMEs in the code for better error checking when versions shouldn't be used. rdar://11457025 llvm-svn: 157019
* Remove incorrect pattern for ARM SMML instruction.Tim Northover2012-05-171-2/+1
| | | | | | Patch by Meador Inge. llvm-svn: 156989
* Allow MCCodeEmitter access to the target MCRegisterInfo.Jim Grosbach2012-05-152-0/+3
| | | | | | | | Add the MCRegisterInfo to the factories and constructors. Patch by Tom Stellard <Tom.Stellard@amd.com>. llvm-svn: 156828
* Fix use of uninitialized variable.David Blaikie2012-05-141-1/+1
| | | | | | Found by GCC's maybe-uninitialized. llvm-svn: 156780
* [fast-isel] Add support for selecting @llvm.trap().Chad Rosier2012-05-111-0/+4
| | | | llvm-svn: 156646
* [fast-isel] Remove -disable-arm-fast-isel option. -fast-isel=0 suffices. ↵Chad Rosier2012-05-111-12/+2
| | | | | | Minor cleanup. llvm-svn: 156632
* [fast-isel] Cleaner fix for when we're unable to handle a non-double multi-regChad Rosier2012-05-111-4/+21
| | | | | | | | retval. Hoists check before emitting the call to avoid unnecessary work. rdar://11430407 PR12796 llvm-svn: 156628
* [fast-isel] Rather then assert (or segfault in a non-asserts build), fall backChad Rosier2012-05-111-2/+4
| | | | | | | | to selection DAG isel if we're unable to handle a non-double multi-reg retval. rdar://11430407 PR12796 llvm-svn: 156622
* The return type is an unsigned, not a bool.Chad Rosier2012-05-111-1/+1
| | | | llvm-svn: 156621
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