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* Only 64-bit targets support TImode libcalls. Disable the TImode shift libcallsBob Wilson2009-05-221-0/+5
| | | | | | for ARM. This fixes rdar://6908807. llvm-svn: 72269
* Minor formatting fixes.Bob Wilson2009-05-201-2/+2
| | | | llvm-svn: 72172
* Fix pr4227: Handle large immediate values in inline assembly.Bob Wilson2009-05-191-1/+1
| | | | llvm-svn: 72138
* Follow up on new support for memory operands in ARM inline assembly.Bob Wilson2009-05-191-0/+4
| | | | | | This fixes pr4233. llvm-svn: 72115
* Fix pr4058 and pr4059. Do not split i64 or double arguments between r3 andBob Wilson2009-05-191-1/+4
| | | | | | the stack. Patch by Sandeep Patel. llvm-svn: 72106
* Fix pr4091: Add support for "m" constraint in ARM inline assembly.Bob Wilson2009-05-192-0/+34
| | | | llvm-svn: 72105
* Fix pr4202: Disable CodePlacementOpt for ARM. The ARMConstantIslandPass hasBob Wilson2009-05-181-1/+4
| | | | | | | | | to run last because it needs to know the exact size and position of every basic block. Currently CodePlacementOpt is set up to run last. It might be worthwhile to investigate reordering these passes, but for now, let's just make it work. llvm-svn: 72037
* Update the names of the exception handling sjlj instrinsics toJim Grosbach2009-05-144-14/+16
| | | | | | | | | llvm.eh.sjlj.* for better clarity as to their purpose and scope. Add a description of llvm.eh.sjlj.setjmp to ExceptionHandling.html. (llvm.eh.sjlj.longjmp documentation coming when that implementation is added). llvm-svn: 71758
* Spelling correction s/builting/builtin/ and remove trailing whitespace in a ↵Jim Grosbach2009-05-131-10/+10
| | | | | | few places llvm-svn: 71735
* Run code placement optimization for targets that want it (arm and x86 for now).Evan Cheng2009-05-131-0/+1
| | | | llvm-svn: 71726
* Change MachineInstrBuilder::addReg() to take a flag instead of a list ofBill Wendling2009-05-133-37/+38
| | | | | | | | | | | | booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). llvm-svn: 71722
* Add support for GCC compatible builtin setjmp and longjmp intrinsics. This isJim Grosbach2009-05-124-4/+52
| | | | | | | a supporting preliminary patch for GCC-compatible SjLJ exception handling. Note that these intrinsics are not designed to be invoked directly by the user, but rather used by the front-end as target hooks for exception handling. llvm-svn: 71610
* correct register class for tADDspi to GPR since the register will always be SPJim Grosbach2009-05-121-1/+1
| | | | llvm-svn: 71602
* Fix up a few minor typos in comments.Bob Wilson2009-05-121-7/+7
| | | | llvm-svn: 71563
* Fix 80-col violations and remove trailing whitespace. No functional changes.Bob Wilson2009-05-121-69/+71
| | | | llvm-svn: 71562
* Rename PaddedSize to AllocSize, in the hope that thisDuncan Sands2009-05-092-2/+2
| | | | | | | will make it more obvious what it represents, and stop it being confused with the StoreSize. llvm-svn: 71349
* Instead of passing in an unsigned value for the optimization level, use an enum,Bill Wendling2009-04-294-18/+31
| | | | | | | which better identifies what the optimization is doing. And is more flexible for future uses. llvm-svn: 70440
* Second attempt:Bill Wendling2009-04-294-24/+28
| | | | | | | | | | | | Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to use the old behavior, the flag is -O0. This change allows for finer-grained control over which optimizations are run at different -O levels. Most of this work was pretty mechanical. The majority of the fixes came from verifying that a "fast" variable wasn't used anymore. The JIT still uses a "Fast" flag. I'll change the JIT with a follow-up patch. llvm-svn: 70343
* r70270 isn't ready yet. Back this out. Sorry for the noise.Bill Wendling2009-04-284-28/+24
| | | | llvm-svn: 70275
* Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want toBill Wendling2009-04-284-24/+28
| | | | | | | | | | | use the old behavior, the flag is -O0. This change allows for finer-grained control over which optimizations are run at different -O levels. Most of this work was pretty mechanical. The majority of the fixes came from verifying that a "fast" variable wasn't used anymore. The JIT still uses a "Fast" flag. I'm not 100% sure if it's necessary to change it there... llvm-svn: 70270
* Change LowerCallResult method so that CCValAssign::BCvt can be used withBob Wilson2009-04-251-16/+16
| | | | | | f64 types. This is not used for anything yet. llvm-svn: 70006
* Adjust a comment to reflect what the code does. Splitting a 64-bit argumentBob Wilson2009-04-241-1/+1
| | | | | | | between registers and the stack may be required with the APCS ABI, but it isn't tied to using a particular version of the ARM architecture. llvm-svn: 69978
* Fix up some problems with getCopyToReg and getCopyFromReg nodes beingBob Wilson2009-04-241-8/+12
| | | | | | | | | chained and "flagged" together. I also made a few changes to handle the chain and flag values more consistently. I found these problems by inspection so I'm not aware of anything that breaks because of them (thus no testcase). llvm-svn: 69977
* Remove unnecessary references to f32 types. After specifying that f32Bob Wilson2009-04-241-4/+4
| | | | | | | should be bit-converted to i32, it is sufficient to list only i32 in subsequent definitions. llvm-svn: 69973
* Move duplicated AddLiveIn function from X86 and ARM backends to be a methodBob Wilson2009-04-201-14/+3
| | | | | | | in the MachineFunction class, renaming it to addLiveIn for consistency with the same method in MachineBasicBlock. Thanks for Anton for suggesting this. llvm-svn: 69615
* Move the AddLiveIn function definition closer to its uses.Bob Wilson2009-04-171-11/+11
| | | | llvm-svn: 69382
* Rearrange code to reduce indentation.Bob Wilson2009-04-171-41/+38
| | | | llvm-svn: 69381
* Clean up formatting, remove trailing whitespace, fix comment typos andBob Wilson2009-04-173-44/+31
| | | | | | punctuation. No functional changes. llvm-svn: 69378
* Use CallConvLower.h and TableGen descriptions of the calling conventionsBob Wilson2009-04-176-305/+561
| | | | | | for ARM. Patch by Sandeep Patel. llvm-svn: 69371
* Fix PR3795: Apply Dan's suggested fix forBob Wilson2009-04-081-2/+6
| | | | | | ARMTargetLowering::isLegalAddressingMode. llvm-svn: 68619
* PR2985 / <rdar://problem/6584986>Jim Grosbach2009-04-077-194/+318
| | | | | | | | | | When compiling in Thumb mode, only the low (R0-R7) registers are available for most instructions. Breaking the low registers into a new register class handles this. Uses of R12, SP, etc, are handled explicitly where needed with copies inserted to move results into low registers where the rest of the code generator can deal with them. llvm-svn: 68545
* Handle 'a' modifier in ARM inline assembly.Bob Wilson2009-04-061-0/+3
| | | | | | Patch by Richard Pennington. llvm-svn: 68464
* Wrap some lines to fix indentation problems.Bob Wilson2009-04-031-30/+36
| | | | llvm-svn: 68405
* Fix some comments.Bob Wilson2009-04-031-5/+5
| | | | llvm-svn: 68404
* Fix PR3862: Recognize some ARM-specific constraints for immediates in inlineBob Wilson2009-04-012-0/+145
| | | | | | assembly. llvm-svn: 68218
* Fix comment to match function name.Bob Wilson2009-03-301-1/+1
| | | | llvm-svn: 68050
* remove trailing whitespaceJim Grosbach2009-03-271-8/+8
| | | | llvm-svn: 67874
* tADDhirr is a thumb instruction. Do not allow this code to be reached in ↵Evan Cheng2009-03-261-0/+2
| | | | | | non-thumb mode. llvm-svn: 67765
* CodeGen still defaults to non-verbose asm, but llc now overrides it and ↵Evan Cheng2009-03-254-15/+16
| | | | | | default to verbose. llvm-svn: 67668
* Do not emit comments unless -asm-verbose.Evan Cheng2009-03-241-8/+18
| | | | llvm-svn: 67580
* Fix a few more indentation problems and an 80-column violation.Bob Wilson2009-03-201-8/+8
| | | | llvm-svn: 67416
* No functional changes. Fix indentation and whitespace only.Bob Wilson2009-03-201-101/+91
| | | | llvm-svn: 67412
* Fix some significant problems with constant pools that resulted in ↵Evan Cheng2009-03-133-13/+13
| | | | | | | | | | | | | | | | | | | | | | | unnecessary paddings between constant pool entries, larger than necessary alignments (e.g. 8 byte alignment for .literal4 sections), and potentially other issues. 1. ConstantPoolSDNode alignment field is log2 value of the alignment requirement. This is not consistent with other SDNode variants. 2. MachineConstantPool alignment field is also a log2 value. 3. However, some places are creating ConstantPoolSDNode with alignment value rather than log2 values. This creates entries with artificially large alignments, e.g. 256 for SSE vector values. 4. Constant pool entry offsets are computed when they are created. However, asm printer group them by sections. That means the offsets are no longer valid. However, asm printer uses them to determine size of padding between entries. 5. Asm printer uses expensive data structure multimap to track constant pool entries by sections. 6. Asm printer iterate over SmallPtrSet when it's emitting constant pool entries. This is non-deterministic. Solutions: 1. ConstantPoolSDNode alignment field is changed to keep non-log2 value. 2. MachineConstantPool alignment field is also changed to keep non-log2 value. 3. Functions that create ConstantPool nodes are passing in non-log2 alignments. 4. MachineConstantPoolEntry no longer keeps an offset field. It's replaced with an alignment field. Offsets are not computed when constant pool entries are created. They are computed on the fly in asm printer and JIT. 5. Asm printer uses cheaper data structure to group constant pool entries. 6. Asm printer compute entry offsets after grouping is done. 7. Change JIT code to compute entry offsets on the fly. llvm-svn: 66875
* Move 3 "(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))"Chris Lattner2009-03-121-1/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | related transformations out of target-specific dag combine into the ARM backend. These were added by Evan in r37685 with no testcases and only seems to help ARM (e.g. test/CodeGen/ARM/select_xform.ll). Add some simple X86-specific (for now) DAG combines that turn things like cond ? 8 : 0 -> (zext(cond) << 3). This happens frequently with the recently added cp constant select optimization, but is a very general xform. For example, we now compile the second example in const-select.ll to: _test: movsd LCPI2_0, %xmm0 ucomisd 8(%esp), %xmm0 seta %al movzbl %al, %eax movl 4(%esp), %ecx movsbl (%ecx,%eax,4), %eax ret instead of: _test: movl 4(%esp), %eax leal 4(%eax), %ecx movsd LCPI2_0, %xmm0 ucomisd 8(%esp), %xmm0 cmovbe %eax, %ecx movsbl (%ecx), %eax ret This passes multisource and dejagnu. llvm-svn: 66779
* It makes no sense to have a ODR version of commonDuncan Sands2009-03-111-2/+1
| | | | | | linkage, so remove it. llvm-svn: 66690
* fix PR3785, a valgrind error on test/CodeGen/ARM/pr3502.llChris Lattner2009-03-111-1/+5
| | | | llvm-svn: 66660
* ARM target now also recognize triplets like thumbv6-apple-darwin and set ↵Evan Cheng2009-03-092-14/+24
| | | | | | thumb mode and arch subversion. Eventually thumb triplets will go way and replaced with function notes. llvm-svn: 66435
* ARM isLegalAddressImmediate should check if type is a simple type now that ↵Evan Cheng2009-03-091-0/+3
| | | | | | optimizer can create values of funky scalar types. llvm-svn: 66429
* Recognize triplets starting with armv5-, armv6- etc. And set the ARM arch ↵Evan Cheng2009-03-081-1/+17
| | | | | | version accordingly. llvm-svn: 66365
* Introduce new linkage types linkonce_odr, weak_odr, common_odrDuncan Sands2009-03-072-7/+12
| | | | | | | | | | | | | | | | | | | | | and extern_weak_odr. These are the same as the non-odr versions, except that they indicate that the global will only be overridden by an *equivalent* global. In C, a function with weak linkage can be overridden by a function which behaves completely differently. This means that IP passes have to skip weak functions, since any deductions made from the function definition might be wrong, since the definition could be replaced by something completely different at link time. This is not allowed in C++, thanks to the ODR (One-Definition-Rule): if a function is replaced by another at link-time, then the new function must be the same as the original function. If a language knows that a function or other global can only be overridden by an equivalent global, it can give it the weak_odr linkage type, and the optimizers will understand that it is alright to make deductions based on the function body. The code generators on the other hand map weak and weak_odr linkage to the same thing. llvm-svn: 66339
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