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* Change enum type in a static table to uint8_t instead. Saves about 700 ↵Craig Topper2012-09-201-6/+6
| | | | | | hundred bytes of static data. Change unsigned char in same table to uint8_t for explicitness. llvm-svn: 164285
* MOVi16 (movw) is only legal on cpus with V6T2 support. rdar://12300648Evan Cheng2012-09-181-2/+4
| | | | llvm-svn: 164169
* When creating MCAsmBackend pass the CPU string as well. In X86AsmBackendRoman Divacky2012-09-182-2/+2
| | | | | | | | | store this and use it to not emit long nops when the CPU is geode which doesnt support them. Fixes PR11212. llvm-svn: 164132
* More domain conversion; convert VFP VMOVS to NEON instructions in more cases ↵James Molloy2012-09-181-13/+56
| | | | | | - when we may clobber the other S-lane by converting an S to a D instruction, make an effort to work out if the S lane is clobberable or not. llvm-svn: 164114
* TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵Andrew Trick2012-09-181-1/+2
| | | | | | model. llvm-svn: 164092
* Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byteEvan Cheng2012-09-182-5/+42
| | | | | | | | | aligned address. Based on patch by David Peixotto. Also use vld1.64 / vst1.64 with 128-bit alignment to take advantage of alignment hints. rdar://12090772, rdar://12238782 llvm-svn: 164089
* Revert r164061-r164067. Most of the new subtarget emitter.Andrew Trick2012-09-171-2/+1
| | | | | | | I have to work out the Target/CodeGen header dependencies before putting this back. llvm-svn: 164072
* TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵Andrew Trick2012-09-171-1/+2
| | | | | | model. llvm-svn: 164061
* Removed the VMLxForwarding feature for the Cortex-A15 target.Silviu Baranga2012-09-171-2/+1
| | | | llvm-svn: 164030
* Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments.Craig Topper2012-09-151-2/+2
| | | | llvm-svn: 163974
* Implement getNumLDMAddresses and expose through ARMBaseInstrInfo.Andrew Trick2012-09-142-0/+34
| | | | llvm-svn: 163922
* Cortex-A9 instruction-level scheduling machine model.Andrew Trick2012-09-141-3/+594
| | | | | | | | | | | | | | | | | | | | This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
* Fix Doxygen issues:Dmitri Gribenko2012-09-141-1/+1
| | | | | | | | | | * wrap code blocks in \code ... \endcode; * refer to parameter names in paragraphs correctly (\arg is not what most people want -- it starts a new paragraph); * use \param instead of \arg to document parameters in order to be consistent with the rest of the codebase. llvm-svn: 163902
* This patch introduces A15 as a target in LLVM.Silviu Baranga2012-09-139-30/+41
| | | | llvm-svn: 163803
* Rename the isMemory() function to isMem(). No functional change intended.Chad Rosier2012-09-111-22/+22
| | | | llvm-svn: 163654
* Remove redundant semicolons which are null statements.Dmitri Gribenko2012-09-101-1/+1
| | | | llvm-svn: 163547
* Don't attempt to use flags from predicated instructions.Jakob Stoklund Olesen2012-09-101-2/+8
| | | | | | | | | | | | The ARM backend can eliminate cmp instructions by reusing flags from a nearby sub instruction with similar arguments. Don't do that if the sub is predicated - the flags are not written unconditionally. <rdar://problem/12263428> llvm-svn: 163535
* Set operation action for FFLOOR to Expand for all vector types for X86. Set ↵Craig Topper2012-09-081-0/+1
| | | | | | FFLOOR of v4f32 to Expand for ARM. v2f64 was already correct. llvm-svn: 163458
* Custom DAGCombine for and/or/xor are for all ARMs.Jakob Stoklund Olesen2012-09-071-6/+3
| | | | | | | The 'select' transformations apply to all ARM architectures and don't require hasV6T2Ops. llvm-svn: 163396
* MC: Overhaul handling of .lcommBenjamin Kramer2012-09-071-1/+0
| | | | | | | | | | | | | - Darwin lied about not supporting .lcomm and turned it into zerofill in the asm parser. Push the zerofill-conversion down into macho-specific code. - This makes the tri-state LCOMMType enum superfluous, there are no targets without .lcomm. - Do proper error reporting when trying to use .lcomm with alignment on a target that doesn't support it. - .comm and .lcomm alignment was parsed in bytes on COFF, should be power of 2. - Fixes PR13755 (.lcomm crashes on ELF). llvm-svn: 163395
* Diagnose invalid alignments on duplicating VLDn instructions.Tim Northover2012-09-061-0/+4
| | | | | | Patch by Chris Lidbury. llvm-svn: 163323
* Check for invalid alignment values when decoding VLDn/VSTn (single ln) ↵Tim Northover2012-09-061-8/+38
| | | | | | | | instructions. Patch by Chris Lidbury. llvm-svn: 163321
* Use correct part of complex operand to encode VST1 alignment.Tim Northover2012-09-061-2/+2
| | | | | | Patch by Chris Lidbury. llvm-svn: 163318
* Fix a few old-GCC warnings. No functional change.Nadav Rotem2012-09-061-1/+1
| | | | llvm-svn: 163309
* Fix self-host; ensure signedness is consistent.James Molloy2012-09-061-2/+2
| | | | llvm-svn: 163306
* Improve codegen for BUILD_VECTORs on ARM.James Molloy2012-09-061-10/+56
| | | | | | If we have a BUILD_VECTOR that is mostly a constant splat, it is often better to splat that constant then insertelement the non-constant lanes instead of insertelementing every lane from an undef base. llvm-svn: 163304
* Optimize codegen for VSETLNi{8,16,32} operating on Q registers. Degenerate ↵James Molloy2012-09-062-17/+66
| | | | | | to a VSETLN on D registers, instead of an (INSERT_SUBREG (VSETLN (EXTRACT_SUBREG ))) sequence to help the register coalescer. llvm-svn: 163298
* Remove predicated pseudo-instructions.Jakob Stoklund Olesen2012-09-052-100/+0
| | | | | | | These pseudos are no longer needed now that it is possible to represent predicated instructions in SSA form. llvm-svn: 163275
* Use predication instead of pseudo-opcodes when folding into MOVCC.Jakob Stoklund Olesen2012-09-051-56/+31
| | | | | | | | | | | | | | | | | | | | Now that it is possible to dynamically tie MachineInstr operands, predicated instructions are possible in SSA form: %vreg3<def> = SUBri %vreg1, -2147483647, pred:14, pred:%noreg, %opt:%noreg %vreg4<def,tied1> = MOVCCr %vreg3<tied0>, %vreg1, %pred:12, pred:%CPSR Becomes a predicated SUBri with a tied imp-use: SUBri %vreg1, -2147483647, pred:13, pred:%CPSR, opt:%noreg, %vreg1<imp-use,tied0> This means that any instruction that is safe to move can be folded into a MOVCC, and the *CC pseudo-instructions are no longer needed. The test case changes reflect that Thumb2SizeReduce recognizes the predicated instructions. It didn't understand the pseudos. llvm-svn: 163274
* Stop casting away const qualifier needlessly.Roman Divacky2012-09-051-1/+1
| | | | llvm-svn: 163258
* Strip old MachineInstrs *after* we know we can put them back.Tim Northover2012-09-051-6/+6
| | | | | | | | Previous patch accidentally decided it couldn't convert a VFP to a NEON instruction after it had already destroyed the old one. Not a good move. llvm-svn: 163230
* Fix function name per coding standard.Chad Rosier2012-09-051-2/+2
| | | | llvm-svn: 163187
* Patch to implement UMLAL/SMLAL instructions for the ARM architectureArnold Schwaighofer2012-09-045-17/+251
| | | | | | | | | | | This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! llvm-svn: 163136
* [ms-inline asm] Asm operands can map to one or more MCOperands. Therefore, addChad Rosier2012-09-031-2/+2
| | | | | | | the NumMCOperands argument to the GetMCInstOperandNum() function that is set to the number of MCOperands this asm operand mapped to. llvm-svn: 163124
* [ms-inline asm] Add an interface to the GetMCInstOperandNum() function in theChad Rosier2012-09-031-0/+6
| | | | | | MCTargetAsmParser class. llvm-svn: 163122
* Removed unused argument.Chad Rosier2012-09-031-2/+1
| | | | llvm-svn: 163104
* [ms-inline asm] Expose the Kind and Opcode variables from theChad Rosier2012-09-031-1/+4
| | | | | | | | | | MatchInstructionImpl() function. These values are used by the ConvertToMCInst() function to index into the ConversionTable. The values are also needed to call the GetMCInstOperandNum() function. llvm-svn: 163101
* Not all targets have efficient ISel code generation for select instructions.Nadav Rotem2012-09-021-0/+5
| | | | | | | | | For example, the ARM target does not have efficient ISel handling for vector selects with scalar conditions. This patch adds a TLI hook which allows the different targets to report which selects are supported well and which selects should be converted to CF duting codegen prepare. llvm-svn: 163093
* Limit domain conversion to cases where it won't break dep chains.Tim Northover2012-09-011-12/+48
| | | | | | | | NEON domain conversion was too heavy-handed with its widened registers, which could have stripped existing instructions of their dependency, leaving them vulnerable to scheduling errors. llvm-svn: 163070
* Fix Thumb2 fixup kind in the integrated-as.Logan Chien2012-09-011-0/+4
| | | | llvm-svn: 163063
* Remove an unused argument. The MCInst opcode is set in the ConvertToMCInst()Chad Rosier2012-08-311-47/+42
| | | | | | function nowadays. llvm-svn: 163030
* Add a comment to explain what's really going on.Chad Rosier2012-08-311-0/+6
| | | | llvm-svn: 163005
* The ConvertToMCInst() function can't fail, so remove the now dead ↵Chad Rosier2012-08-311-3/+0
| | | | | | Match_ConversionFail enum. llvm-svn: 163002
* Fix a couple of typos in EmitAtomic.Jakob Stoklund Olesen2012-08-311-2/+2
| | | | | | | | | Thumb2 instructions are mostly constrained to rGPR, not tGPR which is for Thumb1. rdar://problem/12203728 llvm-svn: 162968
* With the fix in r162954/162955 every cvt function returns true. Thus, haveChad Rosier2012-08-311-64/+42
| | | | | | | the ConvertToMCInst() return void, rather then a bool. Update all the cvt functions as well. llvm-svn: 162961
* Fix for r162954. Return the Error.Chad Rosier2012-08-301-2/+2
| | | | llvm-svn: 162955
* Move a check to the validateInstruction() function where it more properly ↵Chad Rosier2012-08-301-11/+13
| | | | | | belongs. llvm-svn: 162954
* Typo.Chad Rosier2012-08-301-1/+1
| | | | llvm-svn: 162952
* Add support for moving pure S-register to NEON pipeline if desiredTim Northover2012-08-301-2/+71
| | | | llvm-svn: 162898
* Refactor setExecutionDomain to be clearer about what it's doing and more robust.Tim Northover2012-08-291-45/+53
| | | | llvm-svn: 162844
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