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* Change ForceSizeOpt attribute into MinSize attributeQuentin Colombet2012-10-301-4/+4
| | | | llvm-svn: 167020
* ARM: Better disassembly for pc-relative LDR.Jim Grosbach2012-10-304-4/+6
| | | | | | | | | When the operand is a plain immediate rather than a label, print it as [pc, #imm] like we do for the Thumb2 wide encoding variant. rdar://12154503 llvm-svn: 166991
* Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch targetKevin Enderby2012-10-292-11/+23
| | | | | | | is 24 bits not 20 and the decoding needed to correctly handle converting the J1 and J2 bits to their I1 and I2 values to reconstruct the displacement. llvm-svn: 166982
* Remove TargetELFWriterInfo.Rafael Espindola2012-10-285-149/+0
| | | | | | All the credit goes to Jan Voung for noticing it was dead! llvm-svn: 166902
* [code size][ARM] Emit regular call instructions instead of the move, branch ↵Quentin Colombet2012-10-271-2/+8
| | | | | | sequence llvm-svn: 166854
* Revert r163298 "Optimize codegen for VSETLNi{8,16,32} operating on Q registers."Jakob Stoklund Olesen2012-10-262-66/+17
| | | | | | | Keep the integer_insertelement test case, the new coalescer can handle this kind of lane insertion without help from pseudo-instructions. llvm-svn: 166835
* Avoid an unused-variable warning when asserts are disabled.Kaelyn Uhrain2012-10-261-2/+1
| | | | llvm-svn: 166834
* 80 col.Jakob Stoklund Olesen2012-10-261-2/+4
| | | | llvm-svn: 166818
* Remove ARMBaseRegisterInfo::isReservedReg().Jakob Stoklund Olesen2012-10-263-55/+26
| | | | | | It is just as easy to use MRI::isReserved() now. llvm-svn: 166817
* Add GPRPair Register class to ARM.Jakob Stoklund Olesen2012-10-263-0/+45
| | | | | | | | | Some instructions in ARM require 2 even-odd paired GPRs. This patch adds support for such register class. Patch by Weiming Zhao! llvm-svn: 166816
* Remove the canCombineSubRegIndices() target hook.Jakob Stoklund Olesen2012-10-262-126/+0
| | | | | | | The new coalescer can already do all of this, so there is no need to duplicate the efforts. llvm-svn: 166813
* [ms-inline asm] Add support for creating AsmRewrites in the target specificChad Rosier2012-10-251-2/+4
| | | | | | AsmParser logic. To be used/tested in a subsequent commit. llvm-svn: 166714
* Fix a miscompilation caused by a typo. When turning a adde with negative valueEvan Cheng2012-10-242-7/+7
| | | | | | | | | into a sbc with a positive number, the immediate should be complemented, not negated. Also added a missing pattern for ARM codegen. rdar://12559385 llvm-svn: 166613
* Implement a basic VectorTargetTransformInfo interface to be used by the loop ↵Nadav Rotem2012-10-241-2/+2
| | | | | | and bb vectorizers for modeling the cost of instructions. llvm-svn: 166593
* Add in support for getIntPtrType to get the pointer type based on the ↵Micah Villmow2012-10-241-1/+2
| | | | | | | | | address space. This checkin also adds in some tests that utilize these paths and updates some of the clients. llvm-svn: 166578
* Make branch heavy code for generating marked up disassembly simplerKevin Enderby2012-10-231-304/+142
| | | | | | | and easier to read by adding a couple helper functions. Suggestion by Chandler Carruth and seconded by Meador Inge! llvm-svn: 166515
* When a block ends in an indirect branch, add its successors to the machine ↵Bill Wendling2012-10-221-0/+5
| | | | | | | | | | basic block. The CFG of the machine function needs to know that the targets of the indirect branch are successors to the indirect branch. <rdar://problem/12529625> llvm-svn: 166448
* Add support for annotated disassembly output for X86 and arm.Kevin Enderby2012-10-221-128/+486
| | | | | | | | | | | Per the October 12, 2012 Proposal for annotated disassembly output sent out by Jim Grosbach this set of changes implements this for X86 and arm. The llvm-mc tool now has a -mdis option to produced the marked up disassembly and a couple of small example test cases have been added. rdar://11764962 llvm-svn: 166445
* ARM:Stepan Dyatkovskiy2012-10-192-12/+20
| | | | | | | | Removed extra stack frame object for fixed byval arguments, VarArgsStyleRegisters invocation was reworked due to some improper usage in past. PR14099 also demonstrates it. llvm-svn: 166273
* Reapply the TargerTransformInfo changes, minus the changes to LSR and ↵Nadav Rotem2012-10-182-3/+21
| | | | | | Lowerinvoke. llvm-svn: 166248
* Fix a bug where a 32-bit address with the high bit does not get symbolicatedKevin Enderby2012-10-181-2/+3
| | | | | | | because the value is incorrectly being signed extended when passed to SymbolLookUp(). llvm-svn: 166234
* Temporarily revert the TargetTransform changes.Bob Wilson2012-10-182-21/+3
| | | | | | | | | | | The TargetTransform changes are breaking LTO bootstraps of clang. I am working with Nadav to figure out the problem, but I am reverting it for now to get our buildbots working. This reverts svn commits: 165665 165669 165670 165786 165787 165997 and I have also reverted clang svn 165741 llvm-svn: 166168
* Merge MRI::isPhysRegOrOverlapUsed() into isPhysRegUsed().Jakob Stoklund Olesen2012-10-171-2/+2
| | | | | | | | | | | All callers of these functions really want the isPhysRegOrOverlapUsed() functionality which also checks aliases. For historical reasons, targets without register aliases were calling isPhysRegUsed() instead. Change isPhysRegUsed() to also check aliases, and switch all isPhysRegOrOverlapUsed() callers to isPhysRegUsed(). llvm-svn: 166117
* Issue:Stepan Dyatkovskiy2012-10-162-11/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stack is formed improperly for long structures passed as byval arguments for EABI mode. If we took AAPCS reference, we can found the next statements: A: "If the argument requires double-word alignment (8-byte), the NCRN (Next Core Register Number) is rounded up to the next even register number." (5.5 Parameter Passing, Stage C, C.3). B: "The alignment of an aggregate shall be the alignment of its most-aligned component." (4.3 Composite Types, 4.3.1 Aggregates). So if we have structure with doubles (9 double fields) and 3 Core unused registers (r1, r2, r3): caller should use r2 and r3 registers only. Currently r1,r2,r3 set is used, but it is invalid. Callee VA routine should also use r2 and r3 regs only. All is ok here. This behaviour is guessed by rounding up SP address with ADD+BFC operations. Fix: Main fix is in ARMTargetLowering::HandleByVal. If we detected AAPCS mode and 8 byte alignment, we waste odd registers then. P.S.: I also improved LDRB_POST_IMM regression test. Since ldrb instruction will not generated by current regression test after this patch. llvm-svn: 166018
* ARM: v1i64 and v2i64 VBSL intrinsic support.Jim Grosbach2012-10-151-0/+17
| | | | | | rdar://12502028 llvm-svn: 165981
* Resubmit the changes to llvm core to update the functions to support ↵Micah Villmow2012-10-151-1/+1
| | | | | | different pointer sizes on a per address space basis. llvm-svn: 165941
* Fixed PR13938: the ARM backend was crashing because it couldn't select a ↵Silviu Baranga2012-10-151-2/+19
| | | | | | VDUPLANE node with the vector input size different from the output size. This was bacause the BUILD_VECTOR lowering code didn't check that the size of the input vector was correct for using VDUPLANE. llvm-svn: 165929
* [ms-inline asm] Remove the MatchInstruction() function. Previously, this wasChad Rosier2012-10-131-6/+7
| | | | | | | | | | | the interface between the front-end and the MC layer when parsing inline assembly. Unfortunately, this is too deep into the parsing stack. Specifically, we're unable to handle target-independent assembly (i.e., assembly directives, labels, etc.). Note the MatchAndEmitInstruction() isn't the correct abstraction either. I'll be exposing target-independent hooks shortly, so this is really just a cleanup. llvm-svn: 165858
* ARM: tail-call inside a function where part of a byval argument is on caller'sManman Ren2012-10-121-0/+8
| | | | | | | | | | | | | | | | | | | | | local frame causes problem. For example: void f(StructToPass s) { g(&s, sizeof(s)); } will cause problem with tail-call since part of s is passed via registers and saved in f's local frame. When g tries to access s, part of s may be corrupted since f's local frame is popped out before the tail-call. The current fix is to disable tail-call if getVarArgsRegSaveSize is not 0 for the caller. This is a conservative approach, if we can prove the address of s or part of s is not taken and passed to g, it should be okay to perform tail-call. rdar://12442472 llvm-svn: 165853
* ARM: Mark VSELECT as 'expand'.Jim Grosbach2012-10-121-0/+1
| | | | | | | | | | | | | The backend already pattern matches to form VBSL when it can. We may want to teach it to use the vbsl intrinsics at some point to prevent machine licm from mucking with this, but using the Expand is completely correct. http://llvm.org/bugs/show_bug.cgi?id=13831 http://llvm.org/bugs/show_bug.cgi?id=13961 Patch by Peter Couperus <peter.couperus@st.com>. llvm-svn: 165845
* [ms-inline asm] Use the new API introduced in r165830 in lieu of theChad Rosier2012-10-121-4/+1
| | | | | | MapAndConstraints vector. Also remove the unused Kind argument. llvm-svn: 165833
* Remove unnecessary classof()'sSean Silva2012-10-112-8/+0
| | | | | | | isa<> et al. automatically infer when the cast is an upcast (including a self-cast), so these are no longer necessary. llvm-svn: 165767
* Revert 165732 for further review.Micah Villmow2012-10-111-1/+1
| | | | llvm-svn: 165747
* Add in the first iteration of support for llvm/clang/lldb to allow variable ↵Micah Villmow2012-10-111-1/+1
| | | | | | per address space pointer sizes to be optimized correctly. llvm-svn: 165726
* Add isel patterns for v2f32 / v4f32 neon.vbsl intrinsics. rdar://12471808Evan Cheng2012-10-101-0/+8
| | | | llvm-svn: 165673
* Add a new interface to allow IR-level passes to access codegen-specific ↵Nadav Rotem2012-10-102-3/+21
| | | | | | information. llvm-svn: 165665
* Fix for LDRB instruction:Stepan Dyatkovskiy2012-10-101-1/+2
| | | | | | | | | | | | | | | | | | | SDNode for LDRB_POST_IMM is invalid: number of registers added to SDNode fewer that described in .td. 7 ops is needed, but SDNode with only 6 is created. In more details: In ARMInstrInfo.td, in multiclass AI2_ldridx, in definition _POST_IMM, offset operand is defined as am2offset_imm. am2offset_imm is complex parameter type, and actually it consists from dummy register and imm itself. As I understood trick with dummy reg was made for AsmParser. In ARMISelLowering.cpp, this dummy register was not added to SDNode, and it cause crash in Peephole Optimizer pass. The problem fixed by setting up additional dummy reg when emitting LDRB_POST_IMM instruction. llvm-svn: 165617
* Issue description:Stepan Dyatkovskiy2012-10-102-8/+17
| | | | | | | | | | | | | | | | | | | | SchedulerDAGInstrs::buildSchedGraph ignores dependencies between FixedStack objects and byval parameters. So loading byval parameters from stack may be inserted *before* it will be stored, since these operations are treated as independent. Fix: Currently ARMTargetLowering::LowerFormalArguments saves byval registers with FixedStack MachinePointerInfo. To fix the problem we need to store byval registers with MachinePointerInfo referenced to first the "byval" parameter. Also commit adds two new fields to the InputArg structure: Function's argument index and InputArg's part offset in bytes relative to the start position of Function's argument. E.g.: If function's argument is 128 bit width and it was splitted onto 32 bit regs, then we got 4 InputArg structs with same arg index, but different offset values. llvm-svn: 165616
* misched: Use the TargetSchedModel interface wherever possible.Andrew Trick2012-10-102-16/+0
| | | | | | | | Allows the new machine model to be used for NumMicroOps and OutputLatency. Allows the HazardRecognizer to be disabled along with itineraries. llvm-svn: 165603
* whitespaceAndrew Trick2012-10-101-3/+3
| | | | llvm-svn: 165601
* Use the attribute enums to query if a parameter has an attribute.Bill Wendling2012-10-091-6/+6
| | | | llvm-svn: 165550
* Create enums for the different attributes.Bill Wendling2012-10-094-6/+9
| | | | | | | We use the enums to query whether an Attributes object has that attribute. The opaque layer is responsible for knowing where that specific attribute is stored. llvm-svn: 165488
* In parseMSRMaskOperand, add an explicit check for the operand being an ↵Craig Topper2012-10-091-1/+2
| | | | | | identifier instead of just having an assert. llvm-svn: 165480
* Remove some dead code from ARMAsmPrinter. Add virtual and LLVM_OVERRIDE to ↵Craig Topper2012-10-092-38/+22
| | | | | | the other methods. Mark some of the helper methods as private. llvm-svn: 165479
* Move TargetData to DataLayout.Micah Villmow2012-10-0811-32/+32
| | | | llvm-svn: 165402
* [ms-inline asm] Add a few typedefs to simplify future changes.Chad Rosier2012-10-051-1/+1
| | | | llvm-svn: 165324
* ARM: locate user-defined text sections next to default text.Jim Grosbach2012-10-041-4/+20
| | | | | | | | | | | | Make sure functions located in user specified text sections (via the section attribute) are located together with the default text sections. Otherwise, for large object files, the relocations for call instructions are more likely to be out of range. This becomes even more likely in the presence of LTO. rdar://12402636 llvm-svn: 165254
* Add methods which query for the specific attribute instead of using theBill Wendling2012-10-031-6/+6
| | | | | | enums. This allows for better encapsulation of the Attributes class. llvm-svn: 165132
* [ms-inline asm] Add the convertToMapAndConstraints() function that is used toChad Rosier2012-10-011-2/+4
| | | | | | | | | | | map constraints and MCInst operands to inline asm operands. This replaces the getMCInstOperandNum() function. The logic to determine the constraints are not in place, so we still default to a register constraint (i.e., "r"). Also, we no longer build the MCInst but rather return just the opcode to get the MCInstrDesc. llvm-svn: 164979
* MachO: direct-to-object attribute for data-in-code markers.Jim Grosbach2012-10-011-1/+3
| | | | | | | | | | The target backend can support data-in-code load commands even when the assembler doesn't, or vice-versa. Allow targets to opt-in for direct-to-object. PR13973. llvm-svn: 164974
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