summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM
Commit message (Collapse)AuthorAgeFilesLines
* [FastISel][ARM] Fix a think-o in my previous commit (r215682).Juergen Ributzka2014-08-151-15/+15
| | | | | | | | | We actually need to return the register into which we materialized the constant and not just "true" for success. This code is currently partially dead, that is why it didn't trigger any failures yet. Once I change the order of the constant materialization this code will be fully exercised. llvm-svn: 215727
* Remove HasLEB128.Rafael Espindola2014-08-151-2/+0
| | | | | | We already require CFI, so it should be safe to require .leb128 and .uleb128. llvm-svn: 215712
* ARM: implement MRS/MSR (banked reg) system instructions.Tim Northover2014-08-157-4/+241
| | | | | | | | | | These are system-only instructions for CPUs with virtualization extensions, allowing a hypervisor easy access to all of the various different AArch32 registers. rdar://problem/17861345 llvm-svn: 215700
* [FastISel][ARM] Fall-back to constant pool loads when materializing an i32 ↵Juergen Ributzka2014-08-141-1/+2
| | | | | | | | | | | | | | constant. FastEmit_i won't always succeed to materialize an i32 constant and just fail. This would trigger a fall-back to SelectionDAG, which is really not necessary. This fix will first fall-back to a constant pool load to materialize the constant before giving up for good. This fixes <rdar://problem/18022633>. llvm-svn: 215682
* [FastISel][ARM] Use MOVT/MOVW if the subtarget requests it.Juergen Ributzka2014-08-131-0/+3
| | | | | | | | This change is also in preparation for a future change to make sure that the constant materialization uses MOVT/MOVW when available and not a load from the constant pool. llvm-svn: 215584
* [FastISel][ARM] Fix a bug in the integer materialization code.Juergen Ributzka2014-08-131-1/+3
| | | | | | | | | | | | getRegClassFor returns the incorrect register class when in Thumb2 mode. This fix simply manually selects the register class as in the code just a few lines above. There is no test case for this code, because the code is currently unreachable. This will be changed in a future commit and existing test cases will exercise this code. llvm-svn: 215583
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-1335-77/+82
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* IR: Print a newline when dumping TypesJustin Bogner2014-08-121-1/+1
| | | | | | | | | | | | Type::dump() doesn't print a newline, which makes for a poor experience in a debugger. This looks like it was an ommission considering Value::dump() two lines above, so I've changed Type to add a newline as well. Of the two in-tree callers, one added a newline anyway, and I've updated the other one to use Type::print instead. llvm-svn: 215421
* [ARM] Mark VMOVDRR with the RegSequence property and implement the relatedQuentin Colombet2014-08-113-0/+46
| | | | | | | | | | | | | target hook. This patch teaches the compiler that: dX = VMOVDRR rY, rZ is the same as: dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1 <rdar://problem/12702965> llvm-svn: 215404
* ARM: try harder to detect non-IT eligible instructionsSaleem Abdulrasool2014-08-111-7/+32
| | | | | | | | | | | | | | | | | | | For many Thumb-1 register register instructions, setting the CPSR is not permitted inside an IT block. We would not correctly flag those instructions. The previous change to identify this scenario was insufficient as it did not actually catch all the instances. The current list is formed by manual inspection of the ARMv6M ARM. The change to the Thumb2 IT block test is due to the fact that the new more stringent checking of the MIs results in the If Conversion pass being prevented from executing (since not all the instructions in the BB are predicable). This results in code gen changes. Thanks to Tim Northover for pointing out that the previous patch was insufficient and hinting that the use of the v6M ARM would be much easier to use than the v7 or v8! llvm-svn: 215382
* ARM: __gnu_h2f_ieee and __gnu_f2h_ieee always use the soft-float calling ↵Oliver Stannard2014-08-111-0/+13
| | | | | | | | | | | | convention By default, LLVM uses the "C" calling convention for all runtime library functions. The half-precision FP conversion functions use the soft-float calling convention, and are needed for some targets which use the hard-float convention by default, so must have their calling convention explicitly set. llvm-svn: 215348
* ARM: correct isPredicable for MULS in ThHUMB modeSaleem Abdulrasool2014-08-101-0/+14
| | | | | | | | | | | | | | | | | | The ARM ARM states that CPSR may not be updated by a MUL in thumb mode. Due to an ordering of Thumb 2 Size Reduction and If Conversion, we would end up generating a THUMB MULS inside an IT block. The If Conversion pass uses the TTI isPredicable method to ensure that it can transform a Basic Block. However, because we only check for IT handling on Thumb2 functions, we may miss some cases. Even then, it only validates that the CPSR is not *live* rather than it is not accessed. This corrects the handling for that particular case since the same restriction does not hold on the vast majority of the instructions. This does prevent the IfConversion optimization from kicking in in certain cases, but generating correct code is more valuable. Addresses PR20555. llvm-svn: 215328
* If available, pass down the Fixup object to EvaluateAsRelocatable.Joerg Sonnenberger2014-08-102-8/+5
| | | | | | | At least on PowerPC, the interpretation of certain modifiers depends on the context they appear in. llvm-svn: 215310
* Temporarily Revert "Nuke the old JIT." as it's not quite ready toEric Christopher2014-08-0711-4/+2456
| | | | | | | | | | | be deleted. This will be reapplied as soon as possible and before the 3.6 branch date at any rate. Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reverts commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 215154
* Nuke the old JIT.Rafael Espindola2014-08-0711-2456/+4
| | | | | | | | | I am sure we will be finding bits and pieces of dead code for years to come, but this is a good start. Thanks to Lang Hames for making MCJIT a good replacement! llvm-svn: 215111
* Fix a whole bunch of binary literals which were the wrong size. All were ↵Pete Cooper2014-08-072-3/+3
| | | | | | | | being silently zero extended to the correct width. The commit after this changes { } and 0bxx literals to be of type bits<n> and not int. This means we need to write exactly the right number of bits, and not rely on the values being silently zero extended for us. llvm-svn: 215082
* Remove the target machine from CCState. Previously it was only usedEric Christopher2014-08-062-23/+23
| | | | | | | | | to get the subtarget and that's accessible from the MachineFunction now. This helps clear the way for smaller changes where we getting a subtarget will require passing in a MachineFunction/Function as well. llvm-svn: 214988
* ARM: do not generate BLX instructions on Cortex-M CPUs.Tim Northover2014-08-062-3/+3
| | | | | | | | | Particularly on MachO, we were generating "blx _dest" instructions on M-class CPUs, which don't actually exist. They happen to get fixed up by the linker into valid "bl _dest" instructions (which is why such a massive issue has remained largely undetected), but we shouldn't rely on that. llvm-svn: 214959
* ARM-MachO: materialize callee address correctly on v4t.Tim Northover2014-08-061-1/+4
| | | | llvm-svn: 214958
* Remove a virtual function from TargetMachine. NFC.Rafael Espindola2014-08-051-1/+0
| | | | llvm-svn: 214929
* Re-apply r214881: Fix return sequence on armv4 thumbJonathan Roelofs2014-08-053-20/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts r214893, re-applying r214881 with the test case relaxed a bit to satiate the build bots. POP on armv4t cannot be used to change thumb state (unilke later non-m-class architectures), therefore we need a different return sequence that uses 'bx' instead: POP {r3} ADD sp, #offset BX r3 This patch also fixes an issue where the return value in r3 would get clobbered for functions that return 128 bits of data. In that case, we generate this sequence instead: MOV ip, r3 POP {r3} ADD sp, #offset MOV lr, r3 MOV r3, ip BX lr http://reviews.llvm.org/D4748 llvm-svn: 214928
* Revert r214881 because it broke lots of build-botsJonathan Roelofs2014-08-053-71/+20
| | | | llvm-svn: 214893
* Fix return sequence on armv4 thumbJonathan Roelofs2014-08-053-20/+71
| | | | | | | | | | | | | | | | | | | | | | | | | POP on armv4t cannot be used to change thumb state (unilke later non-m-class architectures), therefore we need a different return sequence that uses 'bx' instead: POP {r3} ADD sp, #offset BX r3 This patch also fixes an issue where the return value in r3 would get clobbered for functions that return 128 bits of data. In that case, we generate this sequence instead: MOV ip, r3 POP {r3} ADD sp, #offset MOV lr, r3 MOV r3, ip BX lr http://reviews.llvm.org/D4748 llvm-svn: 214881
* Specify that the thumb setend and blx <immed> instructions are not valid on ↵Keith Walker2014-08-051-2/+2
| | | | | | an m-class target llvm-svn: 214871
* Define stc2/stc2l/ldc2/ldc2l as thumb2 instructionsKeith Walker2014-08-051-4/+4
| | | | llvm-svn: 214868
* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-0512-93/+54
| | | | | | | | | | | shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. llvm-svn: 214838
* Allow CP10/CP11 operations on ARMv5/v6Renato Golin2014-08-041-3/+7
| | | | | | | | | | | Those registers are VFP/NEON and vector instructions should be used instead, but old cores rely on those co-processors to enable VFP unwinding. This change was prompted by the libc++abi's unwinding routine and is also present in many legacy low-level bare-metal code that we ought to compile/assemble. Fixing bug PR20025 and allowing PR20529 to proceed with a fix in libc++abi. llvm-svn: 214802
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-0424-159/+234
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* [ARM] In dynamic-no-pic mode, ARM's post-RA pseudo expansion was incorrectlyAkira Hatanaka2014-08-023-9/+9
| | | | | | | | | expanding pseudo LOAD_STATCK_GUARD using instructions that are normally used in pic mode. This patch fixes the bug. <rdar://problem/17886592> llvm-svn: 214614
* [SDAG] Let the DAG combiner take care of dead nodes rather than manuallyChandler Carruth2014-08-021-2/+0
| | | | | | | deleting them. This already seems to work, as no tests fail without this. llvm-svn: 214601
* Add a non-const subtarget returning function to the target machineEric Christopher2014-08-011-1/+2
| | | | | | | | | so that we can use it to get the old-style JIT out of the subtarget. This code should be removed when the old-style JIT is removed (imminently). llvm-svn: 214560
* [FastISel][ARM] Do not emit stores for undef arguments.Juergen Ributzka2014-08-011-0/+6
| | | | | | | | This is a followup patch for r214366, which added the same behavior to the AArch64 and X86 FastISel code. This fix reproduces the already existing behavior of SelectionDAG in FastISel. llvm-svn: 214531
* Allow only disassembling of M-class MSR masks that the assembler knows how ↵James Molloy2014-08-011-1/+47
| | | | | | | | | | to assemble back. Note: The current code in DecodeMSRMask() rejects the unpredictable A/R MSR mask '0000' with Fail. The code in the patch follows this style and rejects unpredictable M-class MSR masks also with Fail (instead of SoftFail). If SoftFail is preferred in this case then additional changes to ARMInstPrinter (to print non-symbolic masks) and ARMAsmParser (to parse non-symbolic masks) will be needed. Patch by Petr Pavlu! llvm-svn: 214505
* [ARM] Make the assembler reject unpredictable pre/post-indexed ARM ↵Tilmann Scheller2014-08-011-1/+7
| | | | | | | | LDRB/LDRSB instructions. The ARM ARM prohibits LDRB/LDRSB instructions with writeback into the destination register. With this commit this constraint is now enforced and we stop assembling LDRH/LDRSH instructions with unpredictable behavior. llvm-svn: 214500
* [ARM] Make the assembler reject unpredictable pre/post-indexed ARM ↵Tilmann Scheller2014-08-011-1/+5
| | | | | | | | LDRH/LDRSH instructions. The ARM ARM prohibits LDRH/LDRSH instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling LDRH/LDRSH instructions with unpredictable behavior. llvm-svn: 214499
* [ARM] Make the assembler reject unpredictable pre/post-indexed ARM LDR ↵Tilmann Scheller2014-08-011-0/+13
| | | | | | | | instructions. The ARM ARM prohibits LDR instructions with writeback into the destination register. With this commit this constraint is now enforced and we stop assembling LDR instructions with unpredictable behavior. llvm-svn: 214498
* Make sure no loads resulting from load->switch DAGCombine are marked invariantLouis Gerbarg2014-07-311-1/+1
| | | | | | | | | | | | | | Currently when DAGCombine converts loads feeding a switch into a switch of addresses feeding a load the new load inherits the isInvariant flag of the left side. This is incorrect since invariant loads can be reordered in cases where it is illegal to reoarder normal loads. This patch adds an isInvariant parameter to getExtLoad() and updates all call sites to pass in the data if they have it or false if they don't. It also changes the DAGCombine to use that data to make the right decision when creating the new load. llvm-svn: 214449
* Fix bit initializer which was one bit too long, but worked so long as we ↵Pete Cooper2014-07-311-1/+1
| | | | | | silently dropped the leading 0 llvm-svn: 214372
* ARM: add __aeabi_d2h for truncation on AEABI systemsTim Northover2014-07-291-0/+1
| | | | | | | ARM does actually define the name for this conversion, so we should use it on "-eabi" platforms. llvm-svn: 214176
* ARM: correct handling of features in arch_extensionSaleem Abdulrasool2014-07-271-11/+12
| | | | | | | | | | | | | | | | | | | | | | The subtarget information is the ultimate source of truth for the feature set that is enabled at this point. We would previously not propagate the feature information to the subtarget. While this worked for the most part (features would be enabled/disabled as requested), if another operation that changed the feature bits was encountered (such as a mode switch via a .arm or .thumb directive), we would end up resetting the behaviour of the architectural extensions. Handling this properly requires a slightly more complicated handling. We need to check if the feature is now being toggled. If so, only then do we toggle the features. In return, we no longer have to calculate the feature bits ourselves. The test changes are mostly to the diagnosis, which is now more uniform (a nice side effect!). Add an additional test to ensure that we handle this case properly. Thanks to Nico Weber for alerting me to this issue! llvm-svn: 214057
* ARM: convert loop to range basedSaleem Abdulrasool2014-07-271-14/+14
| | | | | | | Convert a loop to use range based iteration. Rename structure members to help naming, and make structure definition anonymous. NFC. llvm-svn: 214056
* Add alignment value to allowsUnalignedMemoryAccessMatt Arsenault2014-07-273-8/+12
| | | | | | | | | | Rename to allowsMisalignedMemoryAccess. On R600, 8 and 16 byte accesses are mostly OK with 4-byte alignment, and don't need to be split into multiple accesses. Vector loads with an alignment of the element type are not uncommon in OpenCL code. llvm-svn: 214055
* Wrap to 80 columns, no behavior change.Nico Weber2014-07-251-2/+4
| | | | llvm-svn: 213975
* [stack protector] Fix a potential security bug in stack protector where theAkira Hatanaka2014-07-2510-1/+98
| | | | | | | | | | | | | | address of the stack guard was being spilled to the stack. Previously the address of the stack guard would get spilled to the stack if it was impossible to keep it in a register. This patch introduces a new target independent node and pseudo instruction which gets expanded post-RA to a sequence of instructions that load the stack guard value. Register allocator can now just remat the value when it can't keep it in a register. <rdar://problem/12475629> llvm-svn: 213967
* [ARM] Emit ABI_PCS_R9_use build attribute.Amara Emerson2014-07-251-0/+11
| | | | | | | | Patch by Ben Foster! Differential Revision: http://reviews.llvm.org/D4657 llvm-svn: 213944
* [ARM] In thumb mode, emit directive ".code 16" before file level inlineAkira Hatanaka2014-07-251-0/+3
| | | | | | | | | | | | assembly instructions. This is necessary to ensure ARM assembler switches to Thumb mode before it starts assembling the file level inline assembly instructions at the beginning of a .s file. <rdar://problem/17757232> llvm-svn: 213924
* AA metadata refactoring (introduce AAMDNodes)Hal Finkel2014-07-241-1/+1
| | | | | | | | | | | | | | | | | | | | In order to enable the preservation of noalias function parameter information after inlining, and the representation of block-level __restrict__ pointer information (etc.), additional kinds of aliasing metadata will be introduced. This metadata needs to be carried around in AliasAnalysis::Location objects (and MMOs at the SDAG level), and so we need to generalize the current scheme (which is hard-coded to just one TBAA MDNode*). This commit introduces only the necessary refactoring to allow for the introduction of other aliasing metadata types, but does not actually introduce any (that will come in a follow-up commit). What it does introduce is a new AAMDNodes structure to hold all of the aliasing metadata nodes associated with a particular memory-accessing instruction, and uses that structure instead of the raw MDNode* in AliasAnalysis::Location, etc. No functionality change intended. llvm-svn: 213859
* Prune dependency to MC from each target disassembler.NAKAMURA Takumi2014-07-241-1/+1
| | | | llvm-svn: 213856
* [ARM] Make the assembler reject unpredictable pre/post-indexed ARM STRH ↵Tilmann Scheller2014-07-241-0/+2
| | | | | | | | instructions. The ARM ARM prohibits STRH instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling STRH instructions with unpredictable behavior. llvm-svn: 213850
* Update library dependencies.NAKAMURA Takumi2014-07-242-2/+2
| | | | llvm-svn: 213832
OpenPOWER on IntegriCloud