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* ARM Pseudo-ize tBR_JTr.Jim Grosbach2010-11-295-28/+19
| | | | llvm-svn: 120310
* Thumb2 encodings for MSR and MRS.Owen Anderson2010-11-291-10/+24
| | | | llvm-svn: 120309
* Thumb2 encodings for system instructions.Owen Anderson2010-11-291-8/+50
| | | | llvm-svn: 120307
* Thumb2 encodings for branches and IT blocks.Owen Anderson2010-11-291-0/+15
| | | | llvm-svn: 120306
* The ARM BR_JT* pseudos don't need to use the printer jtblock_operand node toJim Grosbach2010-11-291-4/+4
| | | | | | get the pretty-printer. That's handled explicityly by the MC lowering now. llvm-svn: 120305
* I swear I did a make clean and make before committing all this...Michael J. Spencer2010-11-291-1/+1
| | | | llvm-svn: 120304
* Switch ARM BR_JTm and BR_JTr instructions to be MC-expanded pseudos.Jim Grosbach2010-11-293-43/+95
| | | | llvm-svn: 120303
* Add more Thumb encodings.Bill Wendling2010-11-291-12/+30
| | | | llvm-svn: 120279
* More Thumb encodings.Bill Wendling2010-11-291-24/+76
| | | | llvm-svn: 120278
* Add Thumb encodings for REV instructions.Bill Wendling2010-11-291-19/+37
| | | | llvm-svn: 120277
* Add more Thumb encodings.Bill Wendling2010-11-291-24/+58
| | | | llvm-svn: 120272
* Add support for NEON VLD2-dup instructions.Bob Wilson2010-11-288-8/+255
| | | | llvm-svn: 120236
* Another minor refactoring for VLD1DUP instructions.Bob Wilson2010-11-281-22/+20
| | | | | | | The op11_8 field is the same for all of them so put it in the instruction classes instead of specifying it separately for each instruction. llvm-svn: 120234
* Add entry in getTargetNodeName() for ARMISD::VBICIMM.Bob Wilson2010-11-281-1/+2
| | | | llvm-svn: 120233
* Move more PEI-related hooks to TFIAnton Korobeynikov2010-11-274-327/+328
| | | | llvm-svn: 120229
* Move callee-saved regs spills / reloads to TFIAnton Korobeynikov2010-11-278-229/+232
| | | | llvm-svn: 120228
* Refactor. Set alignment bit in VLD1-dup instruction classes.Bob Wilson2010-11-271-25/+17
| | | | llvm-svn: 120197
* Add NEON VLD1-dup instructions (load 1 element to all lanes).Bob Wilson2010-11-275-2/+119
| | | | llvm-svn: 120194
* Fix incorrect scheduling itineraries for NEON vld1/vst1 instructions.Bob Wilson2010-11-272-8/+8
| | | | | | | | I added these instructions recently but I have no idea where these "1" values in the NextCycles field came from. As far as I can tell now, these instruction stages are clearly intended to overlap. llvm-svn: 120193
* MC/Mach-O: Switch to using MachOFormat.h.Daniel Dunbar2010-11-271-3/+4
| | | | | | - I'm leaving MachO.h, because I believe it has external consumers, but I would really like to eliminate it (we have stylistic disagreements with one another). llvm-svn: 120187
* Remove the unused TheTarget member.Rafael Espindola2010-11-261-1/+1
| | | | llvm-svn: 120168
* Move the ARM reloc constants to Support/ELF.hJason W Kim2010-11-232-142/+4
| | | | llvm-svn: 120035
* Recognize sign/zero-extended constant BUILD_VECTORs for VMULL operations.Bob Wilson2010-11-231-13/+109
| | | | | | | We need to check if the individual vector elements are sign/zero-extended values. For now this only handles constants values. Radar 8687140. llvm-svn: 120034
* Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.Wesley Peck2010-11-232-52/+52
| | | | llvm-svn: 119990
* Fix epilogue codegen to avoid leaving the stack pointer in an invalidEvan Cheng2010-11-223-23/+50
| | | | | | | | | | | | | | | | | state. Previously Thumb2 would restore sp from fp like this: mov sp, r7 sub, sp, #4 If an interrupt is taken after the 'mov' but before the 'sub', callee-saved registers might be clobbered by the interrupt handler. Instead, try restoring directly from sp: add sp, #4 Or, if necessary (with VLA, etc.) use a scratch register to compute sp and then restore it: sub.w r4, r7, #8 mov sp, r7 rdar://8465407 llvm-svn: 119977
* Fix a compiler warning about Kind being used uninitializedDuncan Sands2010-11-221-1/+1
| | | | | | when assertions are disabled. llvm-svn: 119962
* Pseudos default to 4byte size, let the instruction size field noticeEric Christopher2010-11-211-1/+3
| | | | | | that branch tables are special. llvm-svn: 119954
* More Thumb encodings.Bill Wendling2010-11-211-25/+82
| | | | llvm-svn: 119940
* Add encoding for ARM "trap" instruction.Bill Wendling2010-11-211-4/+1
| | | | llvm-svn: 119938
* The "trap" instruction is one of this which doesn't have a condition code. HackBill Wendling2010-11-211-2/+5
| | | | | | the code to not add a "condition code" if it's trap. llvm-svn: 119937
* - Give "trap" the correct encoding, at least according to Darwin's assembler.Bill Wendling2010-11-211-3/+10
| | | | | | - Add comments saying where the encodings for other instructions came from. llvm-svn: 119936
* Use by-name rather than by-order operand matching for some NEON encodings.Owen Anderson2010-11-211-34/+34
| | | | llvm-svn: 119923
* BR_JTadd is ARM-only, so use the proper pseudo class to get the predicate.Jim Grosbach2010-11-211-1/+1
| | | | llvm-svn: 119918
* A few more thumb instruction MC encodings.Bill Wendling2010-11-201-16/+38
| | | | llvm-svn: 119913
* Rewrite address handling to use a structure with all the possible addressEric Christopher2010-11-201-11/+76
| | | | | | mode variables. Handle frame indexes in load/store and allocas again. llvm-svn: 119912
* STRH only needs the additional operand, not t2STRH. Also invert conditionalEric Christopher2010-11-201-9/+5
| | | | | | to match the one from the load emitter above. llvm-svn: 119911
* Move some more hooks to TargetFrameInfoAnton Korobeynikov2010-11-204-97/+100
| | | | llvm-svn: 119904
* Add more Thumb add instruction encodings.Bill Wendling2010-11-201-12/+47
| | | | llvm-svn: 119883
* Add Thumb encodings for some add instructions.Bill Wendling2010-11-201-6/+26
| | | | llvm-svn: 119882
* Add more encodings for Thumb instructions.Bill Wendling2010-11-201-15/+30
| | | | llvm-svn: 119881
* Have the getAddrMode3OpValue() function in ARMCodeEmitter.cpp produce the sameBill Wendling2010-11-201-9/+21
| | | | | | value that the one in ARMMCCodeEmitter.cpp does. llvm-svn: 119878
* Fix ARM LDR* post-indexed operand encoding.Jim Grosbach2010-11-191-5/+5
| | | | llvm-svn: 119869
* Encodings for the compare instructions.Bill Wendling2010-11-191-8/+19
| | | | llvm-svn: 119868
* The Vm and Vn register fields must be the same for a register-register vmov.Owen Anderson2010-11-191-2/+6
| | | | llvm-svn: 119867
* Fix a cut-n-paste-error.Evan Cheng2010-11-191-1/+1
| | | | llvm-svn: 119866
* Operand namesJim Grosbach2010-11-191-4/+4
| | | | llvm-svn: 119864
* trailing whitespaceJim Grosbach2010-11-191-16/+16
| | | | llvm-svn: 119863
* Don't need to save piecemeal now.Eric Christopher2010-11-191-4/+2
| | | | llvm-svn: 119862
* Update comment.Eric Christopher2010-11-191-3/+2
| | | | llvm-svn: 119861
* Add encodings for some of the thumb ADD instructions. Tests will come once theBill Wendling2010-11-191-16/+44
| | | | | | asm parser can handle them. llvm-svn: 119860
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