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* Improve 64-subtraction of immediates when parts of the immediate can fitJim Grosbach2010-07-142-11/+40
| | | | | | | | | | | in the literal field of an instruction. E.g., long long foo(long long a) { return a - 734439407618LL; } rdar://7038284 llvm-svn: 108339
* Add missing address register update to t2LDM_RET instruction.Bob Wilson2010-07-141-1/+1
| | | | | | Patch by Brian Lucas. PR7636. llvm-svn: 108332
* A couple potential optimizations inspired by comment 4 in PR6773.Eli Friedman2010-07-141-0/+41
| | | | llvm-svn: 108328
* Add support for NEON VMVN immediate instructions.Bob Wilson2010-07-143-7/+48
| | | | llvm-svn: 108324
* The bits in the cmode field of 32-bit VMOV immediate instructions all dependBob Wilson2010-07-141-2/+2
| | | | | | of the value of the immediate. llvm-svn: 108323
* Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes.Bob Wilson2010-07-141-0/+29
| | | | | | Radar 7373643. llvm-svn: 108303
* Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to representBob Wilson2010-07-133-192/+78
| | | | | | NEON VMOV-immediate instructions. This simplifies some things. llvm-svn: 108275
* Extend the r107852 optimization which turns some fp compare to code sequence ↵Evan Cheng2010-07-133-71/+240
| | | | | | using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0. llvm-svn: 108258
* Add an ARM "feature". Cortex-a8 fp comparison is very slow (> 20 cycles).Evan Cheng2010-07-132-1/+7
| | | | llvm-svn: 108256
* Move NEON "modified immediate" encode/decode into ARMAddressingModes.h toBob Wilson2010-07-134-77/+84
| | | | | | avoid replicated code. llvm-svn: 108227
* Remove some code that doesn't appear to do anything. All the ARM callBob Wilson2010-07-121-5/+0
| | | | | | | | instructions already have implicit defs of LR. The comment suggests that this is intended to fix something like pr6111, but it doesn't really do that either. llvm-svn: 108186
* Convert some tab stops into spaces.Duncan Sands2010-07-123-8/+8
| | | | llvm-svn: 108130
* RISC architectures get their memory operand folding for free.Jakob Stoklund Olesen2010-07-114-320/+0
| | | | | | | | The only folding these load/store architectures can do is converting COPY into a load or store, and the target independent part of foldMemoryOperand already knows how to do that. llvm-svn: 108099
* Make getPhysicalRegisterRegClass non-virtual. Should be able to remove it soon.Rafael Espindola2010-07-112-18/+0
| | | | llvm-svn: 108094
* Replace copyRegToReg with copyPhysReg for ARM.Jakob Stoklund Olesen2010-07-116-146/+84
| | | | llvm-svn: 108078
* Fix va_arg for doubles. With this patch VAARG nodes always contain theRafael Espindola2010-07-111-0/+4
| | | | | | | | | | | | | | | correct alignment information, which simplifies ExpandRes_VAARG a bit. The patch introduces a new alignment information to TargetLoweringInfo. This is needed since the two natural candidates cannot be used: * The 's' in target data: If this is set to the minimal alignment of any argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for example. * The getTransientStackAlignment method. It is possible for an architecture to have argument less aligned than what we maintain the stack pointer. llvm-svn: 108072
* Add parentheses yet again to satisfy GCC's warnings.Chandler Carruth2010-07-101-3/+3
| | | | llvm-svn: 108043
* Automatically fold COPY instructions into stack load/store.Jakob Stoklund Olesen2010-07-091-1/+1
| | | | llvm-svn: 108012
* In the presence of variable sized objects, allocate an emergency spill slot.Jim Grosbach2010-07-091-3/+10
| | | | | | rdar://8131327 llvm-svn: 108008
* Print "dregpair" NEON operands with a space between them, for readability andBob Wilson2010-07-091-1/+1
| | | | | | consistency with other instructions that have lists of register operands. llvm-svn: 107944
* Check for FiniteOnlyFPMath as well.Evan Cheng2010-07-081-1/+1
| | | | llvm-svn: 107904
* The NEONPreAllocPass should never have to assign fixed registers anymore.Bob Wilson2010-07-081-34/+1
| | | | | | This pass can go away entirely soon. llvm-svn: 107892
* For big-endian systems, VLD2/VST2 with 32-bit vector elements will swap theBob Wilson2010-07-081-2/+2
| | | | | | | words within the 64-bit D registers. Use VLD1/VST1 with 64-bit elements instead. llvm-svn: 107890
* Clean up a comment.Bob Wilson2010-07-081-5/+5
| | | | llvm-svn: 107882
* Convert EXTRACT_SUBREG to COPY when emitting machine instrs.Jakob Stoklund Olesen2010-07-081-3/+3
| | | | | | | | | EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead. Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg(). The isMoveInstr hook will be removed later. llvm-svn: 107879
* r107852 is only safe with -enable-unsafe-fp-math to account for +0.0 == -0.0.Evan Cheng2010-07-081-3/+5
| | | | llvm-svn: 107856
* Optimize some vfp comparisons to integer ones. This patch implements the ↵Evan Cheng2010-07-082-10/+48
| | | | | | | | | | | | | | | | | | | | | | | | simplest case when the following conditions are met: 1. The arguments are f32. 2. The arguments are loads and they have no uses other than the comparison. 3. The comparison code is EQ or NE. e.g. vldr.32 s0, [r1] vldr.32 s1, [r0] vcmpe.f32 s1, s0 vmrs apsr_nzcv, fpscr beq LBB0_2 => ldr r1, [r1] ldr r0, [r0] cmp r0, r1 beq LBB0_2 More complicated cases will be implemented in subsequent patches. llvm-svn: 107852
* Changes to ARM tail calls, mostly cosmetic.Dale Johannesen2010-07-083-8/+20
| | | | | | | | | Add explicit testcases for tail calls within the same module. Duplicate some code to humor those who think .w doesn't apply on ARM. Leave this disabled on Thumb1, and add some comments explaining why it's hard and won't gain much. llvm-svn: 107851
* grammarJim Grosbach2010-07-071-1/+1
| | | | llvm-svn: 107831
* Handle cases where the post-RA scheduler may move instructions between theJim Grosbach2010-07-071-6/+21
| | | | | | | | | address calculation instructions leading up to a jump table when we're trying to convert them into a TB[H] instruction in Thumb2. This realistically shouldn't happen much, if at all, for well formed inputs, but it's more correct to handle it. rdar://7387682 llvm-svn: 107830
* grammar and trailing whitespaceJim Grosbach2010-07-071-6/+6
| | | | llvm-svn: 107811
* Split the SDValue out of OutputArg so that SelectionDAG-independentDan Gohman2010-07-072-4/+10
| | | | | | code can do calling-convention queries. This obviates OutputArgReg. llvm-svn: 107786
* Also use REG_SEQUENCE for VTBX instructions.Bob Wilson2010-07-072-24/+30
| | | | llvm-svn: 107743
* Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's whereJim Grosbach2010-07-071-2/+4
| | | | | | they've been tested to work. llvm-svn: 107742
* By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing ratherJim Grosbach2010-07-061-0/+2
| | | | | | | than assuming a target will custom lower them. Targets which do so should exlicitly mark them as having custom lowerings. PR7454. llvm-svn: 107734
* Use REG_SEQUENCE nodes to make the table registers for VTBL instructions beBob Wilson2010-07-062-10/+61
| | | | | | allocated to consecutive registers. llvm-svn: 107730
* Track defs for all aliases in NEONMoveFix.Jakob Stoklund Olesen2010-07-061-2/+2
| | | | | | | This means that an instruction defining an S register will affect the domain of the parent D register. llvm-svn: 107725
* Propagate debug loc.Devang Patel2010-07-061-2/+2
| | | | llvm-svn: 107710
* Represent NEON load/store alignments in bytes, not bits.Bob Wilson2010-07-063-7/+13
| | | | llvm-svn: 107701
* Reapply r107655 with fixes; insert the pseudo instruction intoDan Gohman2010-07-061-21/+31
| | | | | | | the block before calling the expansion hook. And don't put EFLAGS in a mbb's live-in list twice. llvm-svn: 107691
* Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversionRafael Espindola2010-07-061-4/+6
| | | | | | if profitable. llvm-svn: 107673
* Revert r107655.Dan Gohman2010-07-061-31/+21
| | | | llvm-svn: 107668
* Fix a bunch of custom-inserter functions to handle the case whereDan Gohman2010-07-061-21/+31
| | | | | | the pseudo instruction is not at the end of the block. llvm-svn: 107655
* Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill ↵Evan Cheng2010-07-031-8/+5
| | | | | | slots so it's always false. llvm-svn: 107550
* Remove early IT block formation. It's not used.Evan Cheng2010-07-023-213/+6
| | | | llvm-svn: 107513
* Fix incorrect asm-printing of some NEON immediates. Fix weak testcase soBob Wilson2010-07-022-4/+4
| | | | | | | that it checks the immediate values, not just the instructions opcodes. Radar 8110263. llvm-svn: 107487
* ARM function alignments were off by a power of two. svn 83242 changedBob Wilson2010-07-011-1/+1
| | | | | | | | | getFunctionAlignment and the corresponding use of that value in the ARM asm printer, but now we're using the standard asm printer. The result of this was that function alignments were dropped completely for Thumb functions. Radar 8143571. llvm-svn: 107435
* Add support for encoding VDUP (ARM core register) instructions.Bob Wilson2010-06-291-0/+17
| | | | llvm-svn: 107201
* Add support for encoding NEON VMOV (from core register to scalar) instructions.Bob Wilson2010-06-291-6/+19
| | | | | | | The encoding is the same as VMOV (from scalar to core register) except that the operands are in different places. llvm-svn: 107167
* skip dbg_value instructionsJim Grosbach2010-06-291-0/+2
| | | | llvm-svn: 107154
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