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* Change the NEON VDUPfdf and VDUPfqf pseudo-instructions to actually beJim Grosbach2010-10-062-7/+28
| | | | | | pseudo instructions. llvm-svn: 115840
* Add a 'pattern' arg to the ARM PseudoNeonI class.Jim Grosbach2010-10-062-7/+9
| | | | llvm-svn: 115831
* target operand flag values aren't a bitmaskJim Grosbach2010-10-061-2/+2
| | | | llvm-svn: 115798
* - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. ThisEvan Cheng2010-10-069-40/+298
| | | | | | | | | | | | | allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. llvm-svn: 115755
* replace stuff like:Chris Lattner2010-10-061-15/+11
| | | | | | | | | | | | | | let AsmString = !strconcat( !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)), !strconcat("\t", asm)); with: let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm); :) llvm-svn: 115720
* Comment out fastisel debugging message.Eric Christopher2010-10-051-1/+1
| | | | llvm-svn: 115717
* Random cleanup and make the intermediate register in fptosi aEric Christopher2010-10-051-5/+5
| | | | | | | | 32-bit fp reg, not 64-bit. Fixes SingleSource. llvm-svn: 115711
* Increase the number of bits used internally by the ARM target to represent theJim Grosbach2010-10-052-16/+16
| | | | | | addressing mode from four to five. llvm-svn: 115645
* fix MSVC 2010 build.Michael J. Spencer2010-10-051-1/+2
| | | | llvm-svn: 115594
* Cleanup Whitespace.Michael J. Spencer2010-10-051-11/+11
| | | | llvm-svn: 115593
* Jim Asked us to move DataLayout on ARM back to the most specialized classes. DoRafael Espindola2010-10-034-38/+28
| | | | | | | | so and also change X86 for consistency. Investigating if this can be improved a bit. llvm-svn: 115469
* Major changes to Cortex-A9 itinerary.Evan Cheng2010-10-031-211/+251
| | | | | | | | | | | 1. Model dual issues as two FUs. 2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a dependent pipeline on ALU0. The changes do not have much impact on codegen right now. But I plan to make pre-RA scheduler multi-issue aware which should take good advantage of the changes. llvm-svn: 115457
* Start on lowering global addresses.Eric Christopher2010-10-021-2/+43
| | | | llvm-svn: 115390
* PrintSpecial() can go away now.Jim Grosbach2010-10-011-1/+0
| | | | llvm-svn: 115376
* Stub out constant GV handling, fixes C++ eh tests.Eric Christopher2010-10-011-2/+14
| | | | llvm-svn: 115375
* Nuke the rest of the :comment referencesJim Grosbach2010-10-014-14/+10
| | | | llvm-svn: 115373
* Nuke a bunch of no-longer-needed comment-only asm strings.Jim Grosbach2010-10-011-57/+28
| | | | llvm-svn: 115370
* Fix r115332: correctly model AGU / NEON mux.Evan Cheng2010-10-011-133/+266
| | | | llvm-svn: 115365
* Thread the determination of branch prediction hit rates back through the ↵Owen Anderson2010-10-014-13/+19
| | | | | | | | | if-conversion heuristic APIs. For now, stick with a constant estimate of 90% (branch predictors are good!), but we might find that we want to provide more nuanced estimates in the future. llvm-svn: 115364
* Rename the AsmPrinter directory to InstPrinter for those targets that haveJim Grosbach2010-10-016-2/+2
| | | | | | | been MC-ized for assembly printing. MSP430 is mostly so, but still has the asm printer and lowering code in the printer subdir for the moment. llvm-svn: 115360
* Fix scheduling infor for vmovn and vshrn which I broke accidentially.Evan Cheng2010-10-012-2/+2
| | | | llvm-svn: 115354
* Add operand cycles for vldr / vstr.Evan Cheng2010-10-012-8/+17
| | | | llvm-svn: 115353
* Direct calls only for arm fast isel for now.Eric Christopher2010-10-011-2/+3
| | | | llvm-svn: 115350
* NEON scheduling info fix. vmov reg, reg are single cycle instructions.Evan Cheng2010-10-014-15/+39
| | | | llvm-svn: 115344
* Fix thinko on store instructions. Fixes test_indvars failure.Eric Christopher2010-10-011-6/+6
| | | | llvm-svn: 115342
* Make the spelling of the flags for old-style if-conversion heuristics ↵Owen Anderson2010-10-011-4/+4
| | | | | | consistent between ARM and Thumb2. llvm-svn: 115341
* Provide an option to restore old-style if-conversion heuristics for Thumb2.Owen Anderson2010-10-012-0/+35
| | | | llvm-svn: 115339
* Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP ↵Evan Cheng2010-10-011-151/+232
| | | | | | issue are multiplexed. Model it correctly. llvm-svn: 115332
* grammarJim Grosbach2010-10-011-2/+2
| | | | llvm-svn: 115314
* Implement double return values in calls. Fixes Eric Christopher2010-10-011-9/+35
| | | | | | SingleSource/Regression/C/casts.c. llvm-svn: 115246
* Temporarily add a flag to make it easier to compare the new-style ARM ifOwen Anderson2010-09-301-0/+19
| | | | | | conversion heuristics to the old-style ones. llvm-svn: 115239
* Movement and cleanup.Eric Christopher2010-09-301-26/+26
| | | | llvm-svn: 115225
* Start of generalized call support for ARM fast isel.Eric Christopher2010-09-301-4/+146
| | | | llvm-svn: 115203
* Nuke a few more unused asm stringsJim Grosbach2010-09-303-19/+19
| | | | llvm-svn: 115193
* Move getPointerSize() to the base class since it's not dependent on MachOJim Grosbach2010-09-301-8/+4
| | | | | | vs. ELF llvm-svn: 115180
* Remove extraneous ';'Jim Grosbach2010-09-301-2/+2
| | | | llvm-svn: 115176
* The asm strings are never used at all, so just nuke 'em entirely.Jim Grosbach2010-09-303-14/+7
| | | | llvm-svn: 115160
* Adds getPointerSize() to the AsmBackend which will be needed by the final patchKevin Enderby2010-09-301-0/+8
| | | | | | for the dwarf .loc support to emit dwarf line number tables. llvm-svn: 115153
* 80 column fixJim Grosbach2010-09-301-1/+3
| | | | llvm-svn: 115149
* Fix two tiny issues (ARM does not need COFF) and comment sanity.Jason W Kim2010-09-301-2/+1
| | | | llvm-svn: 115147
* trailing whitespaceJim Grosbach2010-09-301-3/+3
| | | | llvm-svn: 115136
* Remove misplaced ';'. Make buildbots happy, hopefully.Jim Grosbach2010-09-301-1/+1
| | | | llvm-svn: 115135
* Tiny patch for proof-of-concept cleanup of ARMAsmPrinter::EmitStartOfAsmFile()Jason W Kim2010-09-301-1/+1
| | | | | | | Small test for sanity check of resulting ARM .s file. Tested against -r115129. llvm-svn: 115133
* Go ahead and jump!Jim Grosbach2010-09-303-40/+7
| | | | | | | Now that the MC lowering handles the expansion of the pseudos, kill the horrible blobs of text. llvm-svn: 115130
* I added a new file ARMAsmBackend which stubs out in similar ways toJason W Kim2010-09-304-0/+153
| | | | | | | | | | the eqv X86 class. For now, I split the ELFARMAsmBackend from the DarwinARMAsmBackend (also mimicking X86) Tested against -r115126 llvm-svn: 115129
* Now that the pseudos that needed this are all custom lowered, we can go backJim Grosbach2010-09-302-9/+1
| | | | | | to an empty PrintSpecial() llvm-svn: 115128
* Nuke it from orbit. It's the only way to be sure.Jim Grosbach2010-09-303-766/+22
| | | | | | (Kill the dead non-MC asm printer for the ARM target.) llvm-svn: 115127
* ARM instruction itinerary fixes:Evan Cheng2010-09-307-315/+475
| | | | | | | | 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. llvm-svn: 115121
* Refactor arm fast isel libcall handling so that pieces can be usedEric Christopher2010-09-291-63/+98
| | | | | | for generic call handling. llvm-svn: 115105
* Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMPEvan Cheng2010-09-294-23/+52
| | | | | | pipeline forwarding path. llvm-svn: 115098
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