summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM
Commit message (Collapse)AuthorAgeFilesLines
...
* [Modules] Move GetElementPtrTypeIterator into the IR library. As itsChandler Carruth2014-03-041-1/+1
| | | | | | | | | name might indicate, it is an iterator over the types in an instruction in the IR.... You see where this is going. Another step of modularizing the support library. llvm-svn: 202815
* [cleanup] Re-sort all the includes with utils/sort_includes.py.Chandler Carruth2014-03-041-2/+2
| | | | llvm-svn: 202811
* Cleaning up a bunch of pre-Visual C++ 2012 build hacks.Yaron Keren2014-03-042-15/+0
| | | | llvm-svn: 202806
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-0212-59/+50
| | | | | | Remove the old functions. llvm-svn: 202636
* Switch all uses of LLVM_OVERRIDE to just use 'override' directly.Craig Topper2014-03-023-24/+22
| | | | llvm-svn: 202621
* Switch all uses of LLVM_FINAL to just use 'final', and remove the macro.Craig Topper2014-03-021-1/+1
| | | | llvm-svn: 202618
* Now that we have C++11, turn simple functors into lambdas and remove a ton ↵Benjamin Kramer2014-03-011-12/+7
| | | | | | | | of boilerplate. No intended functionality change. llvm-svn: 202588
* Provide a target override for the latest regalloc heuristic.Andrew Trick2014-02-272-0/+7
| | | | | | | This is a temporary workaround for native arm linux builds: PR18996: Changing regalloc order breaks "lencod" on native arm linux builds. llvm-svn: 202433
* Debug info: Remove ARMAsmPrinter::EmitDwarfRegOp(). AsmPrinter can nowAdrian Prantl2014-02-272-68/+0
| | | | | | | | | | scan the register file for sub- and super-registers. No functionality change intended. (Tests are updated because the comments in the assembler output are different.) llvm-svn: 202416
* ARMv8 IfConversion must skip narrow instructions that a) define CPSR and b) ↵Artyom Skrobov2014-02-263-16/+39
| | | | | | wouldn't affect CPSR in an IT block llvm-svn: 202257
* ARMAsmParser: whitespaceSaleem Abdulrasool2014-02-231-4/+4
| | | | llvm-svn: 201989
* ARM IAS: support .align without parametersSaleem Abdulrasool2014-02-231-0/+20
| | | | | | | | .align is handled specially on certain targets. .align without any parameters on ARM indicates a default alignment (4). Handle the special case in the target parser, but fall back to the generic parser for the normal version. llvm-svn: 201988
* ARM IAS: support .short and .hwordSaleem Abdulrasool2014-02-231-5/+9
| | | | | | | | This adds support for the .short and its alias .hword for adding literal values into the object file. This is similar to the .word directive, however, rather than inserting a value of 4 bytes, adds a 2-byte value. llvm-svn: 201968
* Move get[S|U]LEB128Size() to LEB128.h.Logan Chien2014-02-221-16/+6
| | | | | | | | | | This commit moves getSLEB128Size() and getULEB128Size() from MCAsmInfo to LEB128.h and removes some copy-and-paste code. Besides, this commit also adds some unit tests for the LEB128 functions. llvm-svn: 201937
* Remove unnecessary copy of array_lengthof.Benjamin Kramer2014-02-201-5/+2
| | | | llvm-svn: 201798
* move getNameWithPrefix and getSymbol to TargetMachine.Rafael Espindola2014-02-191-1/+1
| | | | | | | | | | TargetLoweringBase is implemented in CodeGen, so before this patch we had a dependency fom Target to CodeGen. This would show up as a link failure of llvm-stress when building with -DBUILD_SHARED_LIBS=ON. This fixes pr18900. llvm-svn: 201711
* Add back r201608, r201622, r201624 and r201625Rafael Espindola2014-02-192-9/+9
| | | | | | | | | | | | | | r201608 made llvm corretly handle private globals with MachO. r201622 fixed a bug in it and r201624 and r201625 were changes for using private linkage, assuming that llvm would do the right thing. They all got reverted because r201608 introduced a crash in LTO. This patch includes a fix for that. The issue was that TargetLoweringObjectFile now has to be initialized before we can mangle names of private globals. This is trivially true during the normal codegen pipeline (the asm printer does it), but LTO has to do it manually. llvm-svn: 201700
* Revert r201622 and r201608.Daniel Jasper2014-02-192-9/+9
| | | | | | | This causes the LLVMgold plugin to segfault. More information on the replies to r201608. llvm-svn: 201669
* Fix PR18743.Rafael Espindola2014-02-182-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | The IR @foo = private constant i32 42 is valid, but before this patch we would produce an invalid MachO from it. It was invalid because it would use an L label in a section where the liker needs the labels in order to atomize it. One way of fixing it would be to just reject this IR in the backend, but that would not be very front end friendly. What this patch does is use an 'l' prefix in sections that we know the linker requires symbols for atomizing them. This allows frontends to just use private and not worry about which sections they go to or how the linker handles them. One small issue with this strategy is that now a symbol name depends on the section, which is not available before codegen. This is not a problem in practice. The reason is that it only happens with private linkage, which will be ignored by the non codegen users (llvm-nm and llvm-ar). llvm-svn: 201608
* Rename a DebugLoc variable to DbgLoc and a DataLayout to DL.Rafael Espindola2014-02-181-139/+157
| | | | | | This is quiet a bit less confusing now that TargetData was renamed DataLayout. llvm-svn: 201606
* GlobalMerge: move "-global-merge" option to the pass itself.Tim Northover2014-02-181-6/+1
| | | | | | | It's rather odd to have the flag enabling and disabling this pass only affect a single target. llvm-svn: 201559
* Fix the arm assembler so that this malformed instruction:Kevin Enderby2014-02-171-1/+2
| | | | | | | | | | | | | | | | | | ldrd r6, r7 [r2, #15] simply gives an error and does not triggers an assertion. As Jim points out, the diagnostic is really strange here, but fixing that would be more complicated. The missing comma results in the parser expecting a construct like r2[2], which is the vector index thing the error message is talking about. That's not what the user intended, though, and there's nothing else in the instruction that looks at all like a vector. Yet more fallout from not having a real parser here and trying to do context-free generic matching for addressing modes. rdar://15097243 llvm-svn: 201531
* Use 16 byte stack alignment for NaCl on ARMMark Seaborn2014-02-163-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NaCl's ARM ABI uses 16 byte stack alignment, so set that in ARMSubtarget.cpp. Using 16 byte alignment exposes an issue in code generation in which a varargs function leaves a 4 byte gap between the values of r1-r3 saved to the stack and the following arguments that were passed on the stack. (Previously, this code only needed to support 4 byte and 8 byte alignment.) With this issue, llc generated: varargs_func: sub sp, sp, #16 push {lr} sub sp, sp, #12 add r0, sp, #16 // Should be 20 stm r0, {r1, r2, r3} ldr r0, .LCPI0_0 // Address of va_list add r1, sp, #16 str r1, [r0] bl external_func Fix the bug by checking for "Align > 4". Also simplify the code by using OffsetToAlignment(), and update comments. Differential Revision: http://llvm-reviews.chandlerc.com/D2677 llvm-svn: 201497
* ARM IAS: (partially) support .arch_extension directiveSaleem Abdulrasool2014-02-161-0/+82
| | | | | | | | | | | | This adds a partial implementation of the .arch_extension directive to the integrated ARM assembler. There are a number of limitations to this implementation arising from the target backend support rather than the implementation itself. Namely, iWMMXT (v1 and v2), Maverick, and XScale support is not present in the ARM backend. Currently, there is no check for A-class only (needed for virt), and no ARMv6k detection (needed for os and sec). The remainder of the extensions are fully supported. llvm-svn: 201471
* Generate the DWARF stack frame decode operations in the function prologue ↵Artyom Skrobov2014-02-142-37/+271
| | | | | | | | for ARM/Thumb functions. Patch by Keith Walker! llvm-svn: 201423
* Re-commit: Demote EmitRawText call in AsmPrinter::EmitInlineAsm() and remove ↵Daniel Sanders2014-02-131-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | hasRawTextSupport() call Summary: AsmPrinter::EmitInlineAsm() will no longer use the EmitRawText() call for targets with mature MC support. Such targets will always parse the inline assembly (even when emitting assembly). Targets without mature MC support continue to use EmitRawText() for assembly output. The hasRawTextSupport() check in AsmPrinter::EmitInlineAsm() has been replaced with MCAsmInfo::UseIntegratedAs which when true, causes the integrated assembler to parse inline assembly (even when emitting assembly output). UseIntegratedAs is set to true for targets that consider any failure to parse valid assembly to be a bug. Target specific subclasses generally enable the integrated assembler in their constructor. The default value can be overridden with -no-integrated-as. All tests that rely on inline assembly supporting invalid assembly (for example, those that use mnemonics such as 'foo' or 'hello world') have been updated to disable the integrated assembler. Changes since review (and last commit attempt): - Fixed test failures that were missed due to configuration of local build. (fixes crash.ll and a couple others). - Fixed tests that happened to pass because the local build was on X86 (should fix 2007-12-17-InvokeAsm.ll) - mature-mc-support.ll's should no longer require all targets to be compiled. (should fix ARM and PPC buildbots) - Object output (-filetype=obj and similar) now forces the integrated assembler to be enabled regardless of default setting or -no-integrated-as. (should fix SystemZ buildbots) Reviewers: rafael Reviewed By: rafael CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2686 llvm-svn: 201333
* ARM: remove floating-point patterns for @llvm.arm.neon.vabsTim Northover2014-02-131-3/+0
| | | | | | | The front-end is now generating the generic @llvm.fabs for this operation now, so the extra patterns are no longer needed. llvm-svn: 201314
* Revert r201237+r201238: Demote EmitRawText call in ↵Daniel Sanders2014-02-121-4/+0
| | | | | | | | AsmPrinter::EmitInlineAsm() and remove hasRawTextSupport() call It introduced multiple test failures in the buildbots. llvm-svn: 201241
* Demote EmitRawText call in AsmPrinter::EmitInlineAsm() and remove ↵Daniel Sanders2014-02-121-0/+4
| | | | | | | | | | | | | | | | | | | | | hasRawTextSupport() call Summary: AsmPrinter::EmitInlineAsm() will no longer use the EmitRawText() call for targets with mature MC support. Such targets will always parse the inline assembly (even when emitting assembly). Targets without mature MC support continue to use EmitRawText() for assembly output. The hasRawTextSupport() check in AsmPrinter::EmitInlineAsm() has been replaced with MCAsmInfo::UseIntegratedAs which when true, causes the integrated assembler to parse inline assembly (even when emitting assembly output). UseIntegratedAs is set to true for targets that consider any failure to parse valid assembly to be a bug. Target specific subclasses generally enable the integrated assembler in their constructor. The default value can be overridden with -no-integrated-as. All tests that rely on inline assembly supporting invalid assembly (for example, those that use mnemonics such as 'foo' or 'hello world') have been updated to disable the integrated assembler. Reviewers: rafael Reviewed By: rafael CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2686 llvm-svn: 201237
* Tweak ARM fastcc by adopting these two AAPCS rules:Evan Cheng2014-02-111-0/+7
| | | | | | | | | | | | | | * CPRCs may be allocated to co-processor registers or the stack – they may never be allocated to core registers * When a CPRC is allocated to the stack, all other VFP registers should be marked as unavailable The difference is only noticeable in rare cases where there are a large number of floating point arguments (e.g. 7 doubles + additional float, double arguments). Although it's probably still better to avoid vmov as it can cause stalls in some older ARM cores. The other, more subtle benefit, is to minimize difference between the various calling conventions. rdar://16039676 llvm-svn: 201193
* ARM: Thumb2 LDR(literal) can target SP.Jim Grosbach2014-02-111-1/+1
| | | | | | | | | Fix a slightly overzealous destination register restriction for the 'without .w' alias. Add some explicit testcases. rdar://16033140 llvm-svn: 201173
* ARM: use natural LLVM IR for vshll instructionsTim Northover2014-02-103-36/+27
| | | | | | | | Similarly to the vshrn instructions, these are simple zext/sext + trunc operations. Using normal LLVM IR should allow for better code, and more sharing with the AArch64 backend. llvm-svn: 201093
* ARM: r12 is callee-saved for interrupt handlersOliver Stannard2014-02-101-2/+2
| | | | | | | For A- and R-class processors, r12 is not normally callee-saved, but is for interrupt handlers. See AAPCS, 5.3.1.1, "Use of IP by the linker". llvm-svn: 201089
* ARM: use LLVM IR to represent the vshrn operationTim Northover2014-02-104-14/+17
| | | | | | | | | | vshrn is just the combination of a right shift and a truncate (and the limits on the immediate value actually mean the signedness of the shift doesn't matter). Using that representation allows us to get rid of an ARM-specific intrinsic, share more code with AArch64 and hopefully get better code out of the mid-end optimisers. llvm-svn: 201085
* Use a consistent argument order in TargetLoweringObjectFile.Rafael Espindola2014-02-092-7/+6
| | | | | | | | | These methods normally call each other and it is really annoying if the arguments are in different order. The more common rule was that the arguments specific to call are first (GV, Encoding, Suffix) and the auxiliary objects (Mang, TM) come after. This patch changes the exceptions. llvm-svn: 201044
* Pass the Mangler by reference.Rafael Espindola2014-02-083-4/+4
| | | | | | | It is never null and it is not used in casts, so there is no reason to use a pointer. This matches how we pass TM. llvm-svn: 201025
* Add LLVM_OVERRIDE to a few declarations.Rafael Espindola2014-02-081-6/+8
| | | | llvm-svn: 201022
* Remove dead code.Rafael Espindola2014-02-071-4/+0
| | | | llvm-svn: 201006
* Remove -arm-disable-ehabi optionRenato Golin2014-02-072-13/+2
| | | | llvm-svn: 200988
* LLVM-1163: AAPCS-VFP violation when CPRC allocated to stackOliver Stannard2014-02-071-4/+5
| | | | | | | | | | | | According to the AAPCS, when a CPRC is allocated to the stack, all other VFP registers should be marked as unavailable. I have also modified the rules for allocating non-CPRCs to the stack, to make it more explicit that all GPRs must be made unavailable. I cannot think of a case where the old version would produce incorrect answers, so there is no test for this. llvm-svn: 200970
* Revert r200095 and r200152. It turns out when compiling with -arch armv7 ↵Evan Cheng2014-02-061-3/+4
| | | | | | -mcpu=cortex-m3, the triple would still set iOS as the OS so the hack is still needed. rdar://15984891 llvm-svn: 200937
* Remove const_cast for STI when parsing inline asmDavid Peixotto2014-02-062-4/+3
| | | | | | | | | | | | | | | | | | | | | In a previous commit (r199818) we added a const_cast to an existing subtarget info instead of creating a new one so that we could reuse it when creating the TargetAsmParser for parsing inline assembly. This cast was necessary because we needed to reuse the existing STI to avoid generating incorrect code when the inline asm contained mode-switching directives (e.g. .code 16). The root cause of the failure was that there was an implicit sharing of the STI between the parser and the MCCodeEmitter. To fix a different but related issue, we now explicitly pass the STI to the MCCodeEmitter (see commits r200345-r200351). The const_cast is no longer necessary and we can now create a fresh STI for the inline asm parser to use. Differential Revision: http://llvm-reviews.chandlerc.com/D2709 llvm-svn: 200929
* Just returning false is the default.Rafael Espindola2014-02-061-4/+0
| | | | llvm-svn: 200890
* Add address space argument to allowsUnalignedMemoryAccess.Matt Arsenault2014-02-052-4/+6
| | | | | | | On R600, some address spaces have more strict alignment requirements than others. llvm-svn: 200887
* Remove support for not using .loc directives.Rafael Espindola2014-02-052-4/+4
| | | | | | Clang itself was not using this. The only way to access it was via llc. llvm-svn: 200862
* ARM: Resolve thumb_bl fixup in same MCFragment.Logan Chien2014-02-051-1/+8
| | | | | | | | | | | | | | In Thumb1 mode, bl instruction might be selected for branches between basic blocks in the function if the offset is greater than 2KB. However, this might cause SEGV because the destination symbol is not marked as thumb function and the execution mode will be reset to ARM mode. Since we are sure that these symbols are in the same data fragment, we can simply resolve these local symbols, and don't emit any relocation information for this bl instruction. llvm-svn: 200842
* ARM: Enable use of relocation type tlsldo in debug info for tls data.Kai Nacke2014-02-052-0/+9
| | | | | | | This fixes PR18554. Reviewers: Renato Golin, Keith Walker llvm-svn: 200826
* Use the default values.Rafael Espindola2014-02-042-3/+3
| | | | llvm-svn: 200781
* Fix PR18345: ldr= pseudo instruction produces incorrect code when using in ↵David Peixotto2014-02-045-107/+256
| | | | | | | | | | | | | | | | | | | | | | | | | | inline assembly This patch fixes the ldr-pseudo implementation to work when used in inline assembly. The fix is to move arm assembler constant pools from the ARMAsmParser class to the ARMTargetStreamer class. Previously we kept the assembler generated constant pools in the ARMAsmParser object. This does not work for inline assembly because a new parser object is created for each blob of inline assembly. This patch moves the constant pools to the ARMTargetStreamer class so that the constant pool will remain alive for the entire code generation process. An ARMTargetStreamer class is now required for the arm backend. There was no existing implementation for MachO, only Asm and ELF. Instead of creating an empty MachO subclass, we decided to make the ARMTargetStreamer a non-abstract class and provide default (llvm_unreachable) implementations for the non constant-pool related methods. Differential Revision: http://llvm-reviews.chandlerc.com/D2638 llvm-svn: 200777
* ARM & AArch64: merge NEON absolute compare intrinsicsTim Northover2014-02-041-4/+4
| | | | | | | | There was an extremely confusing proliferation of LLVM intrinsics to implement the vacge & vacgt instructions. This combines them all into two polymorphic intrinsics, shared across both backends. llvm-svn: 200768
OpenPOWER on IntegriCloud