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* Move duplicated AddLiveIn function from X86 and ARM backends to be a methodBob Wilson2009-04-201-14/+3
| | | | | | | in the MachineFunction class, renaming it to addLiveIn for consistency with the same method in MachineBasicBlock. Thanks for Anton for suggesting this. llvm-svn: 69615
* Move the AddLiveIn function definition closer to its uses.Bob Wilson2009-04-171-11/+11
| | | | llvm-svn: 69382
* Rearrange code to reduce indentation.Bob Wilson2009-04-171-41/+38
| | | | llvm-svn: 69381
* Clean up formatting, remove trailing whitespace, fix comment typos andBob Wilson2009-04-173-44/+31
| | | | | | punctuation. No functional changes. llvm-svn: 69378
* Use CallConvLower.h and TableGen descriptions of the calling conventionsBob Wilson2009-04-176-305/+561
| | | | | | for ARM. Patch by Sandeep Patel. llvm-svn: 69371
* Fix PR3795: Apply Dan's suggested fix forBob Wilson2009-04-081-2/+6
| | | | | | ARMTargetLowering::isLegalAddressingMode. llvm-svn: 68619
* PR2985 / <rdar://problem/6584986>Jim Grosbach2009-04-077-194/+318
| | | | | | | | | | When compiling in Thumb mode, only the low (R0-R7) registers are available for most instructions. Breaking the low registers into a new register class handles this. Uses of R12, SP, etc, are handled explicitly where needed with copies inserted to move results into low registers where the rest of the code generator can deal with them. llvm-svn: 68545
* Handle 'a' modifier in ARM inline assembly.Bob Wilson2009-04-061-0/+3
| | | | | | Patch by Richard Pennington. llvm-svn: 68464
* Wrap some lines to fix indentation problems.Bob Wilson2009-04-031-30/+36
| | | | llvm-svn: 68405
* Fix some comments.Bob Wilson2009-04-031-5/+5
| | | | llvm-svn: 68404
* Fix PR3862: Recognize some ARM-specific constraints for immediates in inlineBob Wilson2009-04-012-0/+145
| | | | | | assembly. llvm-svn: 68218
* Fix comment to match function name.Bob Wilson2009-03-301-1/+1
| | | | llvm-svn: 68050
* remove trailing whitespaceJim Grosbach2009-03-271-8/+8
| | | | llvm-svn: 67874
* tADDhirr is a thumb instruction. Do not allow this code to be reached in ↵Evan Cheng2009-03-261-0/+2
| | | | | | non-thumb mode. llvm-svn: 67765
* CodeGen still defaults to non-verbose asm, but llc now overrides it and ↵Evan Cheng2009-03-254-15/+16
| | | | | | default to verbose. llvm-svn: 67668
* Do not emit comments unless -asm-verbose.Evan Cheng2009-03-241-8/+18
| | | | llvm-svn: 67580
* Fix a few more indentation problems and an 80-column violation.Bob Wilson2009-03-201-8/+8
| | | | llvm-svn: 67416
* No functional changes. Fix indentation and whitespace only.Bob Wilson2009-03-201-101/+91
| | | | llvm-svn: 67412
* Fix some significant problems with constant pools that resulted in ↵Evan Cheng2009-03-133-13/+13
| | | | | | | | | | | | | | | | | | | | | | | unnecessary paddings between constant pool entries, larger than necessary alignments (e.g. 8 byte alignment for .literal4 sections), and potentially other issues. 1. ConstantPoolSDNode alignment field is log2 value of the alignment requirement. This is not consistent with other SDNode variants. 2. MachineConstantPool alignment field is also a log2 value. 3. However, some places are creating ConstantPoolSDNode with alignment value rather than log2 values. This creates entries with artificially large alignments, e.g. 256 for SSE vector values. 4. Constant pool entry offsets are computed when they are created. However, asm printer group them by sections. That means the offsets are no longer valid. However, asm printer uses them to determine size of padding between entries. 5. Asm printer uses expensive data structure multimap to track constant pool entries by sections. 6. Asm printer iterate over SmallPtrSet when it's emitting constant pool entries. This is non-deterministic. Solutions: 1. ConstantPoolSDNode alignment field is changed to keep non-log2 value. 2. MachineConstantPool alignment field is also changed to keep non-log2 value. 3. Functions that create ConstantPool nodes are passing in non-log2 alignments. 4. MachineConstantPoolEntry no longer keeps an offset field. It's replaced with an alignment field. Offsets are not computed when constant pool entries are created. They are computed on the fly in asm printer and JIT. 5. Asm printer uses cheaper data structure to group constant pool entries. 6. Asm printer compute entry offsets after grouping is done. 7. Change JIT code to compute entry offsets on the fly. llvm-svn: 66875
* Move 3 "(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))"Chris Lattner2009-03-121-1/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | related transformations out of target-specific dag combine into the ARM backend. These were added by Evan in r37685 with no testcases and only seems to help ARM (e.g. test/CodeGen/ARM/select_xform.ll). Add some simple X86-specific (for now) DAG combines that turn things like cond ? 8 : 0 -> (zext(cond) << 3). This happens frequently with the recently added cp constant select optimization, but is a very general xform. For example, we now compile the second example in const-select.ll to: _test: movsd LCPI2_0, %xmm0 ucomisd 8(%esp), %xmm0 seta %al movzbl %al, %eax movl 4(%esp), %ecx movsbl (%ecx,%eax,4), %eax ret instead of: _test: movl 4(%esp), %eax leal 4(%eax), %ecx movsd LCPI2_0, %xmm0 ucomisd 8(%esp), %xmm0 cmovbe %eax, %ecx movsbl (%ecx), %eax ret This passes multisource and dejagnu. llvm-svn: 66779
* It makes no sense to have a ODR version of commonDuncan Sands2009-03-111-2/+1
| | | | | | linkage, so remove it. llvm-svn: 66690
* fix PR3785, a valgrind error on test/CodeGen/ARM/pr3502.llChris Lattner2009-03-111-1/+5
| | | | llvm-svn: 66660
* ARM target now also recognize triplets like thumbv6-apple-darwin and set ↵Evan Cheng2009-03-092-14/+24
| | | | | | thumb mode and arch subversion. Eventually thumb triplets will go way and replaced with function notes. llvm-svn: 66435
* ARM isLegalAddressImmediate should check if type is a simple type now that ↵Evan Cheng2009-03-091-0/+3
| | | | | | optimizer can create values of funky scalar types. llvm-svn: 66429
* Recognize triplets starting with armv5-, armv6- etc. And set the ARM arch ↵Evan Cheng2009-03-081-1/+17
| | | | | | version accordingly. llvm-svn: 66365
* Introduce new linkage types linkonce_odr, weak_odr, common_odrDuncan Sands2009-03-072-7/+12
| | | | | | | | | | | | | | | | | | | | | and extern_weak_odr. These are the same as the non-odr versions, except that they indicate that the global will only be overridden by an *equivalent* global. In C, a function with weak linkage can be overridden by a function which behaves completely differently. This means that IP passes have to skip weak functions, since any deductions made from the function definition might be wrong, since the definition could be replaced by something completely different at link time. This is not allowed in C++, thanks to the ODR (One-Definition-Rule): if a function is replaced by another at link-time, then the new function must be the same as the original function. If a language knows that a function or other global can only be overridden by an equivalent global, it can give it the weak_odr linkage type, and the optimizers will understand that it is alright to make deductions based on the function body. The code generators on the other hand map weak and weak_odr linkage to the same thing. llvm-svn: 66339
* Fix a bunch of Doxygen syntax issues. Escape special characters,Dan Gohman2009-03-031-1/+1
| | | | | | and put @file directives on their own comment line. llvm-svn: 65920
* Overhaul my earlier submission due to feedback. It's a large patch, but most ofBill Wendling2009-02-244-15/+22
| | | | | | | | | | | | them are generic changes. - Use the "fast" flag that's already being passed into the asm printers instead of shoving it into the DwarfWriter. - Instead of calling "MI->getParent()->getParent()" for every MI, set the machine function when calling "runOnMachineFunction" in the asm printers. llvm-svn: 65379
* Propagate debug loc info through prologue/epilogue.Bill Wendling2009-02-231-4/+8
| | | | llvm-svn: 65298
* Factor out the code to add a MachineOperand to a MachineInstrBuilder.Dan Gohman2009-02-181-18/+4
| | | | llvm-svn: 64891
* GV with null value initializer shouldn't go to BSS if it's meant for a ↵Evan Cheng2009-02-181-1/+3
| | | | | | mergeable strings section. Currently it only checks for Darwin. Someone else please check if it should apply to other targets as well. llvm-svn: 64877
* and one more fileDale Johannesen2009-02-131-64/+92
| | | | llvm-svn: 64430
* Remove refs to non-DebugLoc versions of BuildMI from ARM.Dale Johannesen2009-02-135-23/+40
| | | | llvm-svn: 64429
* Eliminate a couple of non-DebugLoc BuildMI variants.Dale Johannesen2009-02-121-4/+6
| | | | | | Modify callers. llvm-svn: 64409
* fix PR3538 for ARM.Chris Lattner2009-02-121-12/+19
| | | | llvm-svn: 64384
* Move debug loc info along when the spiller creates new instructions.Bill Wendling2009-02-121-36/+65
| | | | llvm-svn: 64342
* Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nastyEvan Cheng2009-02-092-4/+8
| | | | | | | | suprise to some callers, e.g. register coalescer. For now, add an parameter that tells AnalyzeBranch whether it's safe to modify the mbb. A better solution is out there, but I don't have time to deal with it right now. llvm-svn: 64124
* Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowingDan Gohman2009-02-072-2/+2
| | | | | | ScheduleDAG's TLI member to use const. llvm-svn: 64018
* Get rid of the last non-DebugLoc versions of getNode!Dale Johannesen2009-02-071-12/+15
| | | | | | | | | | | | Many targets build placeholder nodes for special operands, e.g. GlobalBaseReg on X86 and PPC for the PIC base. There's no sensible way to associate debug info with these. I've left them built with getNode calls with explicit DebugLoc::getUnknownLoc operands. I'm not too happy about this but don't see a good improvement; I considered adding a getPseudoOperand or something, but it seems to me that'll just make it harder to read. llvm-svn: 63992
* Remove more non-DebugLoc getNode variants. UseDale Johannesen2009-02-061-2/+1
| | | | | | | | getCALLSEQ_{END,START} to permit passing no DebugLoc there. UNDEF doesn't logically have DebugLoc; add getUNDEF to encapsulate this. llvm-svn: 63978
* Remove more non-DebugLoc versions of getNode.Dale Johannesen2009-02-061-41/+53
| | | | llvm-svn: 63969
* Eliminate remaining non-DebugLoc version of getTargetNode.Dale Johannesen2009-02-061-1/+3
| | | | llvm-svn: 63951
* Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.Evan Cheng2009-02-064-7/+8
| | | | llvm-svn: 63938
* get rid of some non-DebugLoc getTargetNode variants.Dale Johannesen2009-02-061-1/+2
| | | | llvm-svn: 63909
* Get rid of one more non-DebugLoc getNode andDale Johannesen2009-02-061-7/+9
| | | | | | | its corresponding getTargetNode. Lots of caller changes. llvm-svn: 63904
* A few more isAsCheapAsAMove.Evan Cheng2009-02-051-2/+2
| | | | llvm-svn: 63852
* Remove non-DebugLoc forms of CopyToReg and CopyFromReg.Dale Johannesen2009-02-041-7/+12
| | | | | | Adjust callers. llvm-svn: 63789
* Remove non-DebugLoc versions of getLoad and getStore.Dale Johannesen2009-02-041-68/+83
| | | | | | Adjust the many callers of those versions. llvm-svn: 63767
* Add some DL propagation to places that didn'tDale Johannesen2009-02-032-14/+14
| | | | | | have it yet. More coming. llvm-svn: 63673
* Create DebugLoc information in FastISel. Several temporary methods wereBill Wendling2009-02-031-1/+1
| | | | | | | created. Specifically, those BuildMIs which use "DebugLoc::getUnknownLoc()". I'll remove them soon. llvm-svn: 63584
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