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* ARM diagnostic when 's' suffix on mnemonic that can't set flags.Jim Grosbach2011-07-141-7/+9
| | | | | | | | For example, "mlss r0, r1, r2, r3". The MLS instruction does not have a flag-setting variant. llvm-svn: 135203
* Add OperandTypes for Thumb branch targets.Benjamin Kramer2011-07-141-0/+3
| | | | llvm-svn: 135199
* Port operand types for ARM and X86 over from EDIS to the .td files.Benjamin Kramer2011-07-141-0/+5
| | | | llvm-svn: 135198
* ARM MCRR/MCRR2 immediate operand range checking.Jim Grosbach2011-07-142-3/+3
| | | | llvm-svn: 135192
* ARM MCR/MCR2 assembly parsing operand constraints.Jim Grosbach2011-07-142-8/+8
| | | | | | | The immediate operands are restricted to 0-7. Enforce that when parsing assembly. llvm-svn: 135189
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-149-16/+8
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* Reorganize ARM assembler aliases.Jim Grosbach2011-07-141-14/+19
| | | | | | | | Consolidate the individual declarations together for ease of reference. This mirrors the organization in X86, as well, so is good for consistency. No functional change. llvm-svn: 135179
* Don't leak operands when putting them into a shift.Benjamin Kramer2011-07-141-1/+1
| | | | llvm-svn: 135169
* Update ARM Assembly of LDM/STM.Jim Grosbach2011-07-141-5/+8
| | | | | | | ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such. Update the parsing/encoding tests accordingly. llvm-svn: 135168
* ARM ISB instruction assembly parsing.Jim Grosbach2011-07-142-3/+7
| | | | | | | The ISB instruction takes an optional operand, just like DMB/DSB. Typically only 'sy' is meaningful. llvm-svn: 135156
* ARM Assembler support for DSB instruction.Jim Grosbach2011-07-141-0/+2
| | | | | | Add instalias for default 'sy' option. Add tests. llvm-svn: 135116
* DMB instalias needs the same predicate as the instruction.Jim Grosbach2011-07-141-1/+1
| | | | llvm-svn: 135112
* ARM Assembler support for DMB instruction.Jim Grosbach2011-07-132-0/+6
| | | | | | | | Flesh out the options supported for the instruction. Shuffle tests a bit and add entries for the rest of the options. Add an alias to handle the default operand of "sy". llvm-svn: 135109
* Update comments. These are for assembler, too.Jim Grosbach2011-07-131-3/+2
| | | | llvm-svn: 135107
* Add a target-indepedent entry to MCInstrDesc to describe the encoded size of ↵Owen Anderson2011-07-138-246/+213
| | | | | | an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
* ARM Assembler support for DBG instruction.Jim Grosbach2011-07-132-5/+3
| | | | | | Add range checking and testing for parsing and encoding of DBG instruction. llvm-svn: 135102
* Revert 135093. Think-o.Jim Grosbach2011-07-131-2/+2
| | | | llvm-svn: 135094
* Correct range for thumb co-processor immediateJim Grosbach2011-07-131-2/+2
| | | | llvm-svn: 135093
* Range checking for CDP[2] immediates.Jim Grosbach2011-07-134-12/+50
| | | | llvm-svn: 135092
* Cleanup Thumb co-processor instructions a bit.Jim Grosbach2011-07-131-79/+35
| | | | | | Combine redundant base classes and such. No indended functional change. llvm-svn: 135085
* Parameterize away the ARM T1Cop class.Jim Grosbach2011-07-132-13/+12
| | | | llvm-svn: 135082
* Fix predicates for Thumb co-processor instructions.Jim Grosbach2011-07-133-104/+95
| | | | | | | They're all Thumb2 only, not just some of them. More refactoring cleanup coming. llvm-svn: 135081
* Fix encoding for ARM BXJ instruction.Jim Grosbach2011-07-131-3/+5
| | | | llvm-svn: 135077
* Fix encoding of predicate bits on ARM BX_pred.Jim Grosbach2011-07-131-3/+2
| | | | llvm-svn: 135076
* Range checking for 16-bit immediates in ARM assembly.Jim Grosbach2011-07-132-1/+17
| | | | llvm-svn: 135071
* Give the ARM BKPT instruction the right operand type.Jim Grosbach2011-07-131-5/+4
| | | | | | The immediate is of limited range and the operand type should reflect that. llvm-svn: 135066
* Add tests for ARM parsing of 'BKPT' instruction.Jim Grosbach2011-07-131-2/+1
| | | | llvm-svn: 135063
* Improve ARM assembly parsing diagnostics a bit.Jim Grosbach2011-07-131-21/+33
| | | | | | | | | Catch potential cascading errors on a malformed so_reg operand and bail after the first error. Add some tests for the diagnostics we do want. llvm-svn: 135055
* Destination register operand is optional for ADC and SBC ARM.Jim Grosbach2011-07-131-5/+24
| | | | llvm-svn: 135052
* Flesh out ARM Parser support for shifted-register operands.Jim Grosbach2011-07-133-8/+105
| | | | | | | Now works for parsing register shifted register and register shifted immediate arithmetic instructions, including the 'rrx' rotate with extend. llvm-svn: 135049
* 80 columns.Jim Grosbach2011-07-131-4/+5
| | | | llvm-svn: 135047
* Update MCParsedAsmOperand debug methods.Jim Grosbach2011-07-131-2/+2
| | | | | | | | | | | Update the debug output interface for MCParsedAsmOperand to have a print() method which takes an output stream argument, an << operator which invokes the print method using the given stream, and a dump() method which prints the operand to the dbgs() stream. This makes the interface more consistent with the rest of LLVM, and more convenient to use at the debugger command line. llvm-svn: 135043
* Add an entry.Evan Cheng2011-07-131-0/+18
| | | | llvm-svn: 135024
* Improve codegen for select's:Evan Cheng2011-07-132-1/+67
| | | | | | | | | | | | | | | | | | | | if (x != 0) x = 1 if (x == 1) x = 1 Previous codegen looks like this: mov r1, r0 cmp r1, #1 mov r0, #0 moveq r0, #1 The naive lowering select between two different values. It should recognize the test is equality test so it's more a conditional move rather than a select: cmp r0, #1 movne r0, #0 rdar://9758317 llvm-svn: 135017
* Second attempt at de-constifying LLVM Types in FunctionType::get(),Jay Foad2011-07-121-2/+2
| | | | | | StructType::get() and TargetData::getIntPtrType(). llvm-svn: 134982
* Revert r134893 and r134888 (and related patches in other trees). It was causingBill Wendling2011-07-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | an assert on Darwin llvm-gcc builds. Assertion failed: (castIsValid(op, S, Ty) && "Invalid cast!"), function Create, file /Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.llvm-gcc-i386-darwin9-RA/llvm.src/lib/VMCore/Instructions.cpp, li\ ne 2067. etc. http://smooshlab.apple.com:8013/builders/llvm-gcc-i386-darwin9-RA/builds/2354 --- Reverse-merging r134893 into '.': U include/llvm/Target/TargetData.h U include/llvm/DerivedTypes.h U tools/bugpoint/ExtractFunction.cpp U unittests/Support/TypeBuilderTest.cpp U lib/Target/ARM/ARMGlobalMerge.cpp U lib/Target/TargetData.cpp U lib/VMCore/Constants.cpp U lib/VMCore/Type.cpp U lib/VMCore/Core.cpp U lib/Transforms/Utils/CodeExtractor.cpp U lib/Transforms/Instrumentation/ProfilingUtils.cpp U lib/Transforms/IPO/DeadArgumentElimination.cpp U lib/CodeGen/SjLjEHPrepare.cpp --- Reverse-merging r134888 into '.': G include/llvm/DerivedTypes.h U include/llvm/Support/TypeBuilder.h U include/llvm/Intrinsics.h U unittests/Analysis/ScalarEvolutionTest.cpp U unittests/ExecutionEngine/JIT/JITTest.cpp U unittests/ExecutionEngine/JIT/JITMemoryManagerTest.cpp U unittests/VMCore/PassManagerTest.cpp G unittests/Support/TypeBuilderTest.cpp U lib/Target/MBlaze/MBlazeIntrinsicInfo.cpp U lib/Target/Blackfin/BlackfinIntrinsicInfo.cpp U lib/VMCore/IRBuilder.cpp G lib/VMCore/Type.cpp U lib/VMCore/Function.cpp G lib/VMCore/Core.cpp U lib/VMCore/Module.cpp U lib/AsmParser/LLParser.cpp U lib/Transforms/Utils/CloneFunction.cpp G lib/Transforms/Utils/CodeExtractor.cpp U lib/Transforms/Utils/InlineFunction.cpp U lib/Transforms/Instrumentation/GCOVProfiling.cpp U lib/Transforms/Scalar/ObjCARC.cpp U lib/Transforms/Scalar/SimplifyLibCalls.cpp U lib/Transforms/Scalar/MemCpyOptimizer.cpp G lib/Transforms/IPO/DeadArgumentElimination.cpp U lib/Transforms/IPO/ArgumentPromotion.cpp U lib/Transforms/InstCombine/InstCombineCompares.cpp U lib/Transforms/InstCombine/InstCombineAndOrXor.cpp U lib/Transforms/InstCombine/InstCombineCalls.cpp U lib/CodeGen/DwarfEHPrepare.cpp U lib/CodeGen/IntrinsicLowering.cpp U lib/Bitcode/Reader/BitcodeReader.cpp llvm-svn: 134949
* Most MCCodeEmitter's don't meed MCContext.Evan Cheng2011-07-111-2/+1
| | | | llvm-svn: 134922
* Fix recognition of ARM 'adcs' mnemonic.Jim Grosbach2011-07-111-23/+26
| | | | | | The 'CS' is not a predication suffix in this case. llvm-svn: 134903
* Simplify printing of ARM shifted immediates.Jim Grosbach2011-07-113-35/+0
| | | | | | | | | Print shifted immediate values directly rather than as a payload+shifter value pair. This makes for more readable output assembly code, simplifies the instruction printer, and is consistent with how Thumb immediates are displayed. llvm-svn: 134902
* De-constify Types in StructType::get() and TargetData::getIntPtrType().Jay Foad2011-07-111-2/+2
| | | | llvm-svn: 134893
* - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng2011-07-113-30/+51
| | | | | | | | | | | | and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884
* Fix <rdar://problem/9751331>.Cameron Zwarich2011-07-111-3/+3
| | | | llvm-svn: 134882
* Use BranchProbability instead of floating points in IfConverter.Jakub Staszak2011-07-102-19/+27
| | | | llvm-svn: 134858
* Change createAsmParser to take a MCSubtargetInfo instead of triple,Evan Cheng2011-07-092-35/+19
| | | | | | | | | CPU, and feature string. Parsing some asm directives can change subtarget state (e.g. .code 16) and it must be reflected in other modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance must be shared. llvm-svn: 134795
* Fix indentation.Evan Cheng2011-07-081-2/+2
| | | | llvm-svn: 134764
* Add support for ARM / Thumb mode switching with .code 16 and .code 32.Evan Cheng2011-07-081-16/+30
| | | | llvm-svn: 134760
* Mark tBRIND as predicable.Jim Grosbach2011-07-081-2/+2
| | | | llvm-svn: 134758
* Pseudo-ize tBRIND.Jim Grosbach2011-07-081-12/+6
| | | | llvm-svn: 134755
* Make tBX_RET and tBX_RET_vararg predicable.Jim Grosbach2011-07-083-7/+10
| | | | | | | | | | The normal tBX instruction is predicable, so there's no reason the pseudos for using it as a return shouldn't be. Gives us some nice code-gen improvements as can be seen by the test changes. In particular, several tests now have to disable if-conversion because it works too well and defeats the test. llvm-svn: 134746
* Add an intrinsic and codegen support for fused multiply-accumulate. The intentCameron Zwarich2011-07-081-0/+3
| | | | | | is to use this for architectures that have a native FMA instruction. llvm-svn: 134742
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