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* ARM thumb assembly parsing for arithmetic flag setting instructions.Jim Grosbach2011-08-163-1/+62
| | | | | | | | | Thumb one requires that many arithmetic instruction forms have an 'S' suffix. For Thumb2, the whether the suffix is required or precluded depends on whether the instruction is in an IT block. Use target parser predicates to check for these sorts of context-sensitive constraints. llvm-svn: 137746
* ARM .align NOP padding uses different encoding pre-ARMv6.Jim Grosbach2011-08-161-14/+37
| | | | | | Patch by Kristof Beyls and James Malloy. llvm-svn: 137723
* Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the ↵Owen Anderson2011-08-153-20/+27
| | | | | | Thumb2 NEON decoding hooks to bring us closer to correctness. llvm-svn: 137686
* MCTargetAsmParser target match predicate support.Jim Grosbach2011-08-151-1/+2
| | | | | | | | Allow a target assembly parser to do context sensitive constraint checking on a potential instruction match. This will be used, for example, to handle Thumb2 IT block parsing. llvm-svn: 137675
* Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM ↵Owen Anderson2011-08-151-0/+15
| | | | | | | | mode. Update tests to reflect this fact. Patch by James Molloy. llvm-svn: 137647
* Remove dead classes.Owen Anderson2011-08-151-33/+0
| | | | llvm-svn: 137643
* Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.Owen Anderson2011-08-151-2/+2
| | | | llvm-svn: 137641
* Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.Owen Anderson2011-08-151-6/+7
| | | | llvm-svn: 137636
* Fix problems decoding the to/from-lane NEON memory instructions, and add a ↵Owen Anderson2011-08-152-4/+486
| | | | | | comprehensive NEON decoding testcase. llvm-svn: 137635
* Update comment to reflect MC target machine refactor.Jim Grosbach2011-08-151-1/+1
| | | | llvm-svn: 137615
* Expand VMOVQQQQ pseudo instructions.Bob Wilson2011-08-131-0/+46
| | | | | | | Apparently we never added code to expand these pseudo instructions, and in over a year, no one has noticed. Our register allocator must be awesome! llvm-svn: 137551
* ARM STR_POST_IMM offset encoding fix in load/store optimizer.Jim Grosbach2011-08-121-13/+10
| | | | | | | | | Tidy up the code a bit and push the definition of the value next to the uses to try to minimize this sort of issue from arising again while I'm at it. rdar://9945172 llvm-svn: 137525
* ARM expansion of pre-indexed store pseudos should maintain memoperands.Jim Grosbach2011-08-121-1/+3
| | | | | | Partial fix for rdar://9945172. llvm-svn: 137513
* Fix some remaining issues with decoding ARM-mode memory instructions, and ↵Owen Anderson2011-08-122-20/+12
| | | | | | add another batch of tests. llvm-svn: 137502
* Fix decoding of ARM-mode STRH.Owen Anderson2011-08-123-0/+6
| | | | llvm-svn: 137499
* Specify fixed bit in the LDRBT encoding, which allows us to distinguish it ↵Owen Anderson2011-08-121-1/+3
| | | | | | from certain USAT16 encodings. llvm-svn: 137494
* Fix decoding of pre-indexed stores.Owen Anderson2011-08-122-0/+43
| | | | llvm-svn: 137487
* Separate decoding for STREXD and LDREXD to make each work better.Owen Anderson2011-08-122-7/+24
| | | | llvm-svn: 137476
* Silence a bunch (but not all) "variable written but not read" warningsDuncan Sands2011-08-123-4/+5
| | | | | | when building with assertions disabled. llvm-svn: 137460
* ARM vector compare to zero instruction assembly parsing support.Jim Grosbach2011-08-111-0/+15
| | | | llvm-svn: 137389
* Remove no-longer-true comments. These are for the assembler, also.Jim Grosbach2011-08-111-52/+24
| | | | llvm-svn: 137375
* ARM STRT assembly parsing and encoding.Jim Grosbach2011-08-112-14/+30
| | | | llvm-svn: 137372
* Make the USAT16 operand decoder auto-generate-able.Owen Anderson2011-08-111-2/+2
| | | | llvm-svn: 137371
* Add another accidentally omitted predicate operand.Owen Anderson2011-08-111-0/+2
| | | | llvm-svn: 137370
* Add missing predicate operand on SMLA and friends.Owen Anderson2011-08-111-0/+2
| | | | llvm-svn: 137368
* ARM load shifted register pre-index fix shift value asm parser encoding.Jim Grosbach2011-08-111-1/+1
| | | | llvm-svn: 137367
* Handle new register classes in Thumb2 mode. Should fix the ARM buildbots.Owen Anderson2011-08-111-2/+4
| | | | llvm-svn: 137364
* Making SEL decodings auto-generate-able.Owen Anderson2011-08-111-2/+2
| | | | llvm-svn: 137363
* Tidy up comment.Jim Grosbach2011-08-111-2/+1
| | | | llvm-svn: 137359
* Fix decoding support for STREXD and LDREXD.Owen Anderson2011-08-112-2/+29
| | | | llvm-svn: 137356
* ARM STRH assembly parsing and encoding.Jim Grosbach2011-08-113-18/+60
| | | | llvm-svn: 137353
* Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.Owen Anderson2011-08-111-0/+4
| | | | llvm-svn: 137347
* Tidy up. Remove unused template parameter.Jim Grosbach2011-08-112-11/+11
| | | | llvm-svn: 137345
* Improve operand validation for Thumb2 addressing modes.Owen Anderson2011-08-111-48/+50
| | | | llvm-svn: 137344
* ARM STRD assembly parsing and encoding.Jim Grosbach2011-08-113-62/+54
| | | | llvm-svn: 137342
* Continue to tighten decoding by performing more operand validation.Owen Anderson2011-08-113-2/+75
| | | | llvm-svn: 137340
* Tidy up.Jim Grosbach2011-08-111-1/+0
| | | | llvm-svn: 137339
* ARM STRBT assembly parsing and encoding.Jim Grosbach2011-08-112-25/+37
| | | | llvm-svn: 137337
* ARM STR(immediate) assembly parsing and encoding.Jim Grosbach2011-08-112-3/+22
| | | | llvm-svn: 137331
* Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.Owen Anderson2011-08-111-0/+2
| | | | llvm-svn: 137325
* Tighten operand decoding of addrmode2 instruction. The offset register ↵Owen Anderson2011-08-112-2/+2
| | | | | | cannot be PC. llvm-svn: 137323
* Correct immediate range for shifter operands. Patch by James Molloy, with ↵Owen Anderson2011-08-112-4/+17
| | | | | | additional encoding fixes added by me. llvm-svn: 137322
* Improve error checking in the new ARM disassembler. Patch by James Molloy.Owen Anderson2011-08-111-116/+159
| | | | llvm-svn: 137320
* ARM push of a single register encodes as pre-indexed STR.Jim Grosbach2011-08-112-0/+23
| | | | | | | Per the ARM ARM, a 'push' of a single register encodes as an STR, not an STM. llvm-svn: 137318
* ARM pop of a single register encodes as post-indexed LDR.Jim Grosbach2011-08-112-0/+38
| | | | | | | Per the ARM ARM, a 'pop' of a single register encodes as an LDR, not an LDM. llvm-svn: 137316
* ARM LDRT assembly parsing and encoding.Jim Grosbach2011-08-102-23/+24
| | | | llvm-svn: 137282
* Tidy up. 80 columns.Jim Grosbach2011-08-101-16/+18
| | | | llvm-svn: 137277
* ARM LDRH(immediate) assembly parsing and encoding support.Jim Grosbach2011-08-102-5/+24
| | | | llvm-svn: 137260
* ARM LDRD(register) assembly parsing and encoding.Jim Grosbach2011-08-102-3/+79
| | | | | | Add support for literal encoding of #-0 along the way. llvm-svn: 137254
* Fix typo. Not quite sure how that slipped in there.Jim Grosbach2011-08-101-3/+3
| | | | llvm-svn: 137245
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