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* Neon does not actually have VLD{234}.64 instructions.Bob Wilson2009-08-063-9/+0
| | | | | | These operations will have to be synthesized from other instructions. llvm-svn: 78263
* Add a new pre-allocation pass to assign adjacent registers for Neon instructionsBob Wilson2009-08-054-1/+142
| | | | | | | | | that have that constraint. This is currently just assigning a fixed set of registers, and it only handles VLDn for n=2,3,4 with DPR registers. I'm going to expand it to handle more operations next; we can make it smarter once everything is working correctly. llvm-svn: 78256
* When using NEON for single-precision FP, the NEON result must be placed in ↵David Goodwin2009-08-053-21/+41
| | | | | | D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns. llvm-svn: 78244
* Remove redundand checks: the only way to have, e.g. f32 RegVT is exactlyAnton Korobeynikov2009-08-051-11/+7
| | | | | | hardfloat case. llvm-svn: 78237
* Unbreak the stuff, this is ugly, but we cannot do better for now with ↵Anton Korobeynikov2009-08-051-5/+4
| | | | | | 'plain' C calling conv. llvm-svn: 78232
* Missed pieces for ARM HardFP ABI.Anton Korobeynikov2009-08-054-24/+41
| | | | | | Patch by Sandeep Patel! llvm-svn: 78225
* Remove some dead code.Daniel Dunbar2009-08-051-4/+0
| | | | llvm-svn: 78219
* Remove a redundant declaration.Bob Wilson2009-08-051-2/+0
| | | | llvm-svn: 78216
* Disable NEON single-precision FP support for Cortex-A8, for now...David Goodwin2009-08-051-1/+1
| | | | llvm-svn: 78209
* Remove dead code. MDNode and MDString are not Constant anymore.Devang Patel2009-08-051-3/+0
| | | | llvm-svn: 78207
* By default, for cortex-a8 use NEON for single-precision FP. David Goodwin2009-08-052-5/+7
| | | | llvm-svn: 78200
* 80 col violations.Evan Cheng2009-08-051-9/+15
| | | | llvm-svn: 78175
* Oops. I didn't mean to commit this piece yet.Bob Wilson2009-08-051-2/+0
| | | | llvm-svn: 78146
* Major calling convention code refactoring.Dan Gohman2009-08-052-108/+112
| | | | | | | | | | | | | | | | | | | Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142
* Don't flush the raw_ostream between each MachineFunction. These flushDan Gohman2009-08-051-2/+0
| | | | | | | | | | | calls were originally put in place because errs() at one time was not unbuffered, and these print routines are commonly used with errs() for debugging. However, errs() is now properly unbuffered, so the flush calls are no longer needed. This significantly reduces the number of write(2) calls for regular asm printing when there are many small functions. llvm-svn: 78137
* Change DAG nodes for Neon VLD2/3/4 operations to return multiple results.Bob Wilson2009-08-054-31/+108
| | | | | | | | | Get rid of yesterday's code to fix the register usage during isel. Select the new DAG nodes to machine instructions. The new pre-alloc pass to choose adjacent registers for these results is not done, so the results of this will generally not assemble yet. llvm-svn: 78136
* Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.Evan Cheng2009-08-043-9/+8
| | | | llvm-svn: 78126
* Replace dregsingle operand modifier with explicit escaped curly brackets.Bob Wilson2009-08-042-4/+2
| | | | | | | For other VLDn and VSTn operations, we need to list the multiple registers explicitly anyway, so there's no point in special-casing this one usage. llvm-svn: 78109
* Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet.Evan Cheng2009-08-043-8/+13
| | | | llvm-svn: 78104
* Add NEON single-precision FP support for fabs and fneg.David Goodwin2009-08-043-6/+22
| | | | llvm-svn: 78101
* In thumb mode, r7 is used as frame register. This fixes pr4681.Evan Cheng2009-08-041-0/+11
| | | | llvm-svn: 78086
* Match common pattern for FNMAC. Add NEON SP support.David Goodwin2009-08-042-0/+6
| | | | llvm-svn: 78085
* Initial support for single-precision FP using NEON. Added "neonfp" attribute ↵David Goodwin2009-08-047-16/+69
| | | | | | to enable. Added patterns for some binary FP operations. llvm-svn: 78081
* Ooops, I was too fast to commit the wrong fix :(Anton Korobeynikov2009-08-041-2/+2
| | | | llvm-svn: 78060
* Fix a typo - this unbreaks llvm-gcc build on armAnton Korobeynikov2009-08-041-2/+2
| | | | llvm-svn: 78059
* Thumb2 does not have ib (increment before) and da (decrement after) forms of ↵Evan Cheng2009-08-041-4/+10
| | | | | | ldm / stm. llvm-svn: 78057
* Remove ARM specific getInlineAsmLength. We'll rely on the simpler (and ↵Evan Cheng2009-08-042-163/+0
| | | | | | faster) generic algorithm for now. If more accurate computation is needed, we'll rely on the disassembler. llvm-svn: 78032
* Load / store multiple pass fixes for Thumb2. Not enabled yet.Evan Cheng2009-08-042-77/+88
| | | | llvm-svn: 78031
* Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. ↵Evan Cheng2009-08-041-2/+9
| | | | | | This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction. llvm-svn: 78030
* Lower Neon VLD* intrinsics to custom DAG nodes, and manually allocate theBob Wilson2009-08-043-1/+74
| | | | | | results to fixed registers. llvm-svn: 78025
* Minor cleanup. No functional changes intended.Bob Wilson2009-08-041-6/+5
| | | | llvm-svn: 78024
* use TLOF to compute the section for a function instead ofChris Lattner2009-08-031-5/+4
| | | | | | replicating the logic manually. llvm-svn: 78011
* convert macho stub emission to use SwitchToSection instead ofChris Lattner2009-08-031-34/+50
| | | | | | textual sections. llvm-svn: 78007
* Lower CONCAT_VECTOR during legalization instead of matching it during isel.Bob Wilson2009-08-032-26/+19
| | | | | | Add a testcase. llvm-svn: 77992
* llvm_report_error already prints "LLVM ERROR:". So stop reporting errors ↵Benjamin Kramer2009-08-031-1/+1
| | | | | | like "LLVM ERROR: llvm: error:" or "LLVM ERROR: ERROR:". llvm-svn: 77971
* These are done.Evan Cheng2009-08-031-8/+0
| | | | llvm-svn: 77949
* Use the i12 variant of load / store opcodes if offset is zero. Now we pass ↵Evan Cheng2009-08-031-1/+5
| | | | | | all of multisource as well. llvm-svn: 77939
* Move most targets TargetMachine constructor to only taking a target triple.Daniel Dunbar2009-08-022-19/+12
| | | | | | - The C, C++, MSIL, and Mips backends still need the module. llvm-svn: 77927
* Normalize Subtarget constructors to take a target triple string instead ofDaniel Dunbar2009-08-023-8/+4
| | | | | | | | | | Module*. Also, dropped uses of TargetMachine where unnecessary. The only target which still takes a TargetMachine& is Mips, I would appreciate it if someone would normalize this to match other targets. llvm-svn: 77918
* move dwarf debug info section selection stuff from TAI toChris Lattner2009-08-021-11/+0
| | | | | | TLOF, unifying all the dwarf targets at the same time. llvm-svn: 77889
* ARM TAI no longer needs a TM, but createTargetAsmInfo() still does.Chris Lattner2009-08-023-22/+11
| | | | llvm-svn: 77878
* Move the getInlineAsmLength virtual method from TAI to TII, whereChris Lattner2009-08-028-175/+173
| | | | | | | | | | the only real caller (GetFunctionSizeInBytes) uses it. The custom ARM implementation of this is basically reimplementing an assembler poorly for negligible gain. It should be removed IMNSHO, but I'll leave that to ARMish folks to decide. llvm-svn: 77877
* turn some templated inline functions into static functions.Chris Lattner2009-08-022-14/+11
| | | | llvm-svn: 77873
* remove the dead ELFTargetAsmInfo.h/cpp file. TargetAsmInfoChris Lattner2009-08-021-1/+0
| | | | | | defaults to being ELF. llvm-svn: 77866
* remove TargetAsmInfo::TM, which is now dead. The basic TAI class now Chris Lattner2009-08-022-3/+3
| | | | | | no longer depends on TM! llvm-svn: 77863
* convert ctors/dtors section to be in TLOF instead ofChris Lattner2009-08-023-9/+40
| | | | | | TAI. llvm-svn: 77842
* REmove dead fields of TAI.Chris Lattner2009-08-012-2/+0
| | | | llvm-svn: 77820
* Workaround a couple of Darwin assembler bugs.Evan Cheng2009-08-013-31/+71
| | | | llvm-svn: 77781
* Split t2MOVCCs since some assemblers do not recognize mov shifted register ↵Evan Cheng2009-08-012-8/+29
| | | | | | alias with predicate. llvm-svn: 77764
* Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the sameEvan Cheng2009-08-015-72/+40
| | | | | | | | | instructions for calls since BL and BLX are always 32-bit long and BX is always 16-bit long. Also, we should be using BLX to call external function stubs. llvm-svn: 77756
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