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* Merge the ARM disassembler header into the implementation file, since it is ↵Owen Anderson2011-09-012-85/+54
| | | | | | not externally exposed. llvm-svn: 138982
* Fix 80 columns violations.Owen Anderson2011-09-011-449/+655
| | | | llvm-svn: 138980
* Don't drop alignment info on local common symbols.Benjamin Kramer2011-09-011-1/+1
| | | | | | | | | | | - On COFF the .lcomm directive has an alignment argument. - On ELF we fall back to .local + .comm Based on a patch by NAKAMURA Takumi. Fixes PR9337, PR9483 and PR10128. llvm-svn: 138976
* Null-initialize to shut up -Wuninitialized warnings.Eli Friedman2011-09-011-1/+1
| | | | llvm-svn: 138974
* ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code.Jim Grosbach2011-09-011-1/+1
| | | | llvm-svn: 138952
* Fix up r137380 based on post-commit review by Jim Grosbach.James Molloy2011-09-011-593/+595
| | | | llvm-svn: 138948
* t2Bcc is allowed to have a predicate without a preceding IT instruction.Owen Anderson2011-09-011-1/+2
| | | | llvm-svn: 138946
* Thumb2 assembly parsing and encoding for ADD(immediate).Jim Grosbach2011-09-012-6/+50
| | | | llvm-svn: 138922
* Fixup for functions that return a bool.Chad Rosier2011-08-311-2/+2
| | | | llvm-svn: 138918
* Static relocation model Thumb jump table interworking.Jim Grosbach2011-08-311-0/+5
| | | | | | | Make sure the low bit of the PC is set when loading an address directly for jump tables in static relocation model. llvm-svn: 138912
* The asm parser currently selects the wrong encoding for non-conditional ↵Owen Anderson2011-08-312-5/+6
| | | | | | Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps. llvm-svn: 138910
* Thumb2 t2Bcc should encode as t2B when condition is 'always'.Jim Grosbach2011-08-311-0/+5
| | | | llvm-svn: 138898
* Fix encoding for tBcc with immediate offset operand.Owen Anderson2011-08-311-1/+5
| | | | llvm-svn: 138889
* When performing instruction selection for LDR_PRE_IMM/LDRB_PRE_IMM, we still ↵Owen Anderson2011-08-311-1/+8
| | | | | | | | need to preserve the sign of the index. This fixes miscompilations of Quicksort in the nightly testsuite, and hopefully others as well. <rdar://problem/10046188> llvm-svn: 138885
* Remove FIXME. Thumb2 MOV instruction will use separate custom tricks.Jim Grosbach2011-08-311-3/+1
| | | | | | | | When we want encoding T3 (the wide encoding), we can explicitly check for that and twiddle the CanAcceptCarrySet accordingly. For now, just correctly handle encodings T1 and T2 when in Thumb2 mode. llvm-svn: 138879
* Fix roundtripping of Thumb BL/BLX instructions with immediate offsets ↵Owen Anderson2011-08-311-3/+31
| | | | | | instead of labels. llvm-svn: 138874
* tBcc is OK to be predicated in Thumb2 outside of IT blocks (obviously).Jim Grosbach2011-08-311-2/+2
| | | | llvm-svn: 138873
* Thumb2 parsing and encoding for ADC(register).Jim Grosbach2011-08-311-1/+22
| | | | | | | Also add instruction aliases for non-.w versions of SBC since they're the same. llvm-svn: 138871
* 64-bit atomic cmpxchg for ARM.Eli Friedman2011-08-314-37/+93
| | | | llvm-svn: 138868
* Tweak Thumb1 ADD encoding selection a bit.Jim Grosbach2011-08-311-2/+5
| | | | | | | | When the destination register of an add immediate instruction is explicitly specified, encoding T1 is preferred, else encoding T2 is preferred. llvm-svn: 138862
* Put VMOVS widening under a command line option, off by default.Jakob Stoklund Olesen2011-08-311-1/+6
| | | | | | | | | | | It appears that our use of the imp-use and imp-def flags with sub-registers is not yet robust enough to support this. The failing test case is complicated, I am working on a reduction. <rdar://problem/10044201> llvm-svn: 138861
* Some minor cleanups for r138845.Eli Friedman2011-08-311-22/+0
| | | | llvm-svn: 138846
* Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next.Eli Friedman2011-08-314-1/+277
| | | | llvm-svn: 138845
* Fix issues with disassembly of IT instructions involving condition codes ↵Owen Anderson2011-08-302-30/+32
| | | | | | other the EQ/NE. Discovered by roundtrip testing. llvm-svn: 138840
* Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather ↵Owen Anderson2011-08-301-1/+4
| | | | | | than labels. llvm-svn: 138837
* Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets ↵Owen Anderson2011-08-301-1/+4
| | | | | | instead of labels. llvm-svn: 138835
* Fix encoding of Thumb1 B instructions with immediate offsets, which is ↵Owen Anderson2011-08-301-1/+4
| | | | | | necessary for round-tripping. llvm-svn: 138834
* Clean up whitespace.Owen Anderson2011-08-301-8/+8
| | | | llvm-svn: 138833
* Follow up to r138791.Evan Cheng2011-08-304-2/+30
| | | | | | | | | | | | Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to call a target hook to adjust the instruction. For ARM, this is used to adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC instructions have implicit def of CPSR (required since it now uses CPSR physical register dependency rather than "glue"). If the carry flag is used, then the target hook will *fill in* the optional operand with CPSR. Otherwise, the hook will remove the CPSR implicit def from the MachineInstr. llvm-svn: 138810
* Change ARM / Thumb2 addc / adde and subc / sube modeling to use physicalEvan Cheng2011-08-307-346/+358
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
* Revert 138781. It's not playing nicely with the immediate forms for ADC.Jim Grosbach2011-08-291-20/+0
| | | | llvm-svn: 138782
* Thumb2 assembler aliases for ADC/SBC w/o the .w suffix.Jim Grosbach2011-08-291-0/+20
| | | | llvm-svn: 138781
* Add missing encoding information for some of the GPR<->FP register moves.Owen Anderson2011-08-291-2/+23
| | | | llvm-svn: 138780
* Thumb2 parsing and encoding for IT blocks.Jim Grosbach2011-08-291-23/+104
| | | | llvm-svn: 138773
* Apply the same fix for the change in LDR_PRE_IMM/LDRB_PRE_IMM operand ↵Owen Anderson2011-08-291-1/+2
| | | | | | encodings to the load-store optimizer that I applied to the instruction selector in r138758. Fixes ary3 from the nightly test suite. llvm-svn: 138766
* Specify an additional fixed bit in the PLD/PLDW/PLI register-register encoding.Owen Anderson2011-08-291-0/+1
| | | | llvm-svn: 138760
* addrmode_imm12 and addrmode2_offset encode their immediate values ↵Owen Anderson2011-08-291-4/+28
| | | | | | differently. Update the manual instruction selection code that was encoding them the addrmode2 way even though LDR_PRE_IMM/LDRB_PRE_IMM had switched to addrmode_imm12. Should fix a number of nightly test failures. llvm-svn: 138758
* Improve handling of #-0 offsets for many more pre-indexed addressing modes.Owen Anderson2011-08-293-6/+15
| | | | llvm-svn: 138754
* Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well ↵Eli Friedman2011-08-291-0/+1
| | | | | | enough to fix properly. llvm-svn: 138751
* Update the load-store optimizer for changes to the operands on LDR_PRE_IMM ↵Owen Anderson2011-08-291-4/+10
| | | | | | and LDRB_PRE_IMM in r138653. llvm-svn: 138746
* Add support for parsing #-0 on non-memory-operand immediate values, and add ↵Owen Anderson2011-08-291-2/+13
| | | | | | a testcase that necessitates it. llvm-svn: 138739
* Silence GCC warnings and make an array const.Benjamin Kramer2011-08-271-3/+3
| | | | llvm-svn: 138706
* Improve encoding support for BLX with immediat eoperands, and fix a BLX ↵Owen Anderson2011-08-264-12/+25
| | | | | | decoding bug this uncovered. llvm-svn: 138675
* Correct encoding of BL with immediate offset.Owen Anderson2011-08-261-5/+10
| | | | llvm-svn: 138673
* ARM assembly parsing tweak for pldw.Jim Grosbach2011-08-261-3/+4
| | | | llvm-svn: 138669
* Spelling fail.Owen Anderson2011-08-261-1/+1
| | | | llvm-svn: 138667
* Thumb2 assembler parsing and encoding of IT instruction.Jim Grosbach2011-08-262-12/+136
| | | | | | | | This handles only the handling of the IT instruction itself, not the processing and validation of the instructions in the IT block. That's next, and will include encoding tests for IT itself. llvm-svn: 138665
* Fix ARM codegen breakage caused by r138653.Owen Anderson2011-08-261-6/+15
| | | | llvm-svn: 138657
* invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We ↵Owen Anderson2011-08-266-19/+96
| | | | | | were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. llvm-svn: 138653
* Update for feedback from Jim.Owen Anderson2011-08-261-3/+3
| | | | llvm-svn: 138642
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