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* Suppress an unused variable warning in -asserts buildsMatt Beaumont-Gay2011-03-241-0/+1
| | | | llvm-svn: 128244
* Handle the added VBICiv*i* NEON instructions, too.Johnny Chen2011-03-241-2/+7
| | | | llvm-svn: 128243
* Plug a leak by ThumbDisassembler::getInstruction(), thanks to Benjamin Kramer!Johnny Chen2011-03-241-3/+1
| | | | llvm-svn: 128241
* T2 Load/Store Multiple:Johnny Chen2011-03-241-1/+1
| | | | | | | These instructions were changed to not embed the addressing mode within the MC instructions We also need to update the corresponding assert stmt. Also add a test case. llvm-svn: 128240
* Plug a leak in the arm disassembler and put the tests back.Benjamin Kramer2011-03-241-3/+2
| | | | llvm-svn: 128238
* Add asm parsing support w/ testcases for strex/ldrex family of instructionsBruno Cardoso Lopes2011-03-246-60/+104
| | | | llvm-svn: 128236
* ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder ↵Johnny Chen2011-03-241-1/+1
| | | | | | | | | was fooled. Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to the more generic ADDri/SUBri instructions, and add a test case for that. llvm-svn: 128234
* The r118201 added support for VORR (immediate). Update ↵Johnny Chen2011-03-241-0/+16
| | | | | | | | ARMDisassemblerCore.cpp to disassemble the VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function. Add a test case. llvm-svn: 128226
* Add comments to the handling of opcode CPS3p to reject invalid instruction ↵Johnny Chen2011-03-241-0/+2
| | | | | | | | encoding, a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range. llvm-svn: 128220
* Nasty bug in ARMBaseInstrInfo::produceSameValue(). The MachineConstantPoolEntryEvan Cheng2011-03-241-5/+12
| | | | | | | | | | | | entries being compared may not be ARMConstantPoolValue. Without checking whether they are ARMConstantPoolValue first, and if the stars and moons are aligned properly, the equality test may return true (when the first few words of two Constants' values happen to be identical) and very bad things can happen. rdar://9125354 llvm-svn: 128203
* CPS3p: Let's reject impossible imod values by returning false from the ↵Johnny Chen2011-03-241-0/+3
| | | | | | | | | | | | | | | | | | | | | | | DisassembleMiscFrm() function. Fixed rdar://problem/9179416 ARM disassembler crash: "Unknown imod operand" (fuzz testing) Opcode=98 Name=CPS3p Format=ARM_FORMAT_MISCFRM(26) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 1: 1: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 1| ------------------------------------------------------------------------------------------------- Before: cpsUnknown imod operand UNREACHABLE executed at /Volumes/data/lldb/llvm/lib/Target/ARM/InstPrinter/../ARMBaseInfo.h:123! After: /Volumes/data/Radar/9179416/mc-input-arm.txt:1:1: warning: invalid instruction encoding 0x93 0x1c 0x2 0xf1 ^ llvm-svn: 128192
* Load/Store Multiple:Johnny Chen2011-03-241-4/+4
| | | | | | | These instructions were changed to not embed the addressing mode within the MC instructions We also need to update the corresponding assert stmt. Also add two test cases. llvm-svn: 128191
* STRT and STRBT was incorrectly tagged as IndexModeNone during the ↵Johnny Chen2011-03-241-2/+2
| | | | | | | | refactorings (r119821). We now tag them as IndexModePost. llvm-svn: 128189
* The r128103 fix to cope with the removal of addressing modes from the MC ↵Johnny Chen2011-03-241-2/+7
| | | | | | | | | | instructions were incomplete. The assert stmt needs to be updated and the operand index incrment is wrong. Fix the bad logic and add some sanity checking to detect bad instruction encoding; and add a test case. llvm-svn: 128186
* Enable GlobalMerge on darwin.Devang Patel2011-03-231-6/+0
| | | | llvm-svn: 128183
* Cmp peephole optimization isn't always safe for signed arithmetics.Evan Cheng2011-03-231-3/+43
| | | | | | | | | | | | | | | | | | | | | int tries = INT_MAX; while (tries > 0) { tries--; } The check should be: subs r4, #1 cmp r4, #0 bgt LBB0_1 The subs can set the overflow V bit when r4 is INT_MAX+1 (which loop canonicalization apparently does in this case). cmp #0 would have cleared it while not changing the N and Z bits. Since BGT is dependent on the V bit, i.e. (N == V) && !Z, it is not safe to eliminate the cmp #0. rdar://9172742 llvm-svn: 128179
* The high bit of a Thumb2 ADR's offset is stored in bit 26, not bit 25.Owen Anderson2011-03-231-1/+1
| | | | | | This fixes 464.h264ref with the integrated assembler. llvm-svn: 128172
* For ARM Disassembler, start a newline to dump the opcode and friends for an ↵Johnny Chen2011-03-221-1/+1
| | | | | | | | instruction. Change inspired by llvm-bug 9530 submitted by Jyun-Yan You. llvm-svn: 128122
* LDRT and LDRBT was incorrectly tagged as IndexModeNone during the ↵Johnny Chen2011-03-221-2/+2
| | | | | | | | | | refactorings (r119821). We now tag them as IndexModePost. This fixed http://llvm.org/bugs/show_bug.cgi?id=9530. llvm-svn: 128113
* A8.6.399 VSTM:Johnny Chen2011-03-221-12/+2
| | | | | | | | | | | VFP Load/Store Multiple Instructions used to embed the IA/DB addressing mode within the MC instruction; that has been changed so that now, for example, VSTMDDB_UPD and VSTMDIA_UPD are two instructions. Update the ARMDisassemblerCore.cpp's DisassembleVFPLdStMulFrm() to reflect the change. Also add a test case. llvm-svn: 128103
* Migrate the fix in r128041 to ARM's fastisel support as well.Eric Christopher2011-03-221-13/+18
| | | | | | Fixes rdar://9169640 llvm-svn: 128100
* Change MRC and MRC2 instructions to model the output register properlyBruno Cardoso Lopes2011-03-223-24/+37
| | | | llvm-svn: 128085
* Avoid -Wunused-variable in -asserts buildsMatt Beaumont-Gay2011-03-221-6/+4
| | | | llvm-svn: 128048
* We need to pass the TargetMachine object to the InstPrinter if we are printingBill Wendling2011-03-212-3/+7
| | | | | | | | | the alias of an InstAlias instead of the thing being aliased. Because we need to know the features that are valid for an InstAlias. This is part of a work-in-progress. llvm-svn: 127986
* Re-apply r127953 with fixes: eliminate empty return block if it has no ↵Evan Cheng2011-03-212-0/+12
| | | | | | predecessors; update dominator tree if cfg is modified. llvm-svn: 127981
* Revert r127953, "SimplifyCFG has stopped duplicating returns into predecessorsDaniel Dunbar2011-03-192-12/+0
| | | | | | to canonicalize IR", it broke a lot of things. llvm-svn: 127954
* SimplifyCFG has stopped duplicating returns into predecessors to canonicalize IREvan Cheng2011-03-192-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | to have single return block (at least getting there) for optimizations. This is general goodness but it would prevent some tailcall optimizations. One specific case is code like this: int f1(void); int f2(void); int f3(void); int f4(void); int f5(void); int f6(void); int foo(int x) { switch(x) { case 1: return f1(); case 2: return f2(); case 3: return f3(); case 4: return f4(); case 5: return f5(); case 6: return f6(); } } => LBB0_2: ## %sw.bb callq _f1 popq %rbp ret LBB0_3: ## %sw.bb1 callq _f2 popq %rbp ret LBB0_4: ## %sw.bb3 callq _f3 popq %rbp ret This patch teaches codegenprep to duplicate returns when the return value is a phi and where the phi operands are produced by tail calls followed by an unconditional branch: sw.bb7: ; preds = %entry %call8 = tail call i32 @f5() nounwind br label %return sw.bb9: ; preds = %entry %call10 = tail call i32 @f6() nounwind br label %return return: %retval.0 = phi i32 [ %call10, %sw.bb9 ], [ %call8, %sw.bb7 ], ... [ 0, %entry ] ret i32 %retval.0 This allows codegen to generate better code like this: LBB0_2: ## %sw.bb jmp _f1 ## TAILCALL LBB0_3: ## %sw.bb1 jmp _f2 ## TAILCALL LBB0_4: ## %sw.bb3 jmp _f3 ## TAILCALL rdar://9147433 llvm-svn: 127953
* Fixed an assert by the ARM disassembler for LDRD_PRE/POST.Johnny Chen2011-03-191-3/+4
| | | | | | | | The relevant instruction table entries were changed sometime ago to no longer take <Rt2> as an operand. Modify ARMDisassemblerCore.cpp to accomodate the change and add a test case. llvm-svn: 127935
* Add support to the ARM asm parser for the register-shifted-register forms of ↵Owen Anderson2011-03-182-26/+94
| | | | | | basic instructions like ADD. More work left to be done to support other instances of shifter ops in the ISA. llvm-svn: 127917
* Match a few more obvious patterns to revsh. rdar://9147637.Evan Cheng2011-03-182-2/+16
| | | | llvm-svn: 127913
* Clean whitespace.Owen Anderson2011-03-181-8/+8
| | | | llvm-svn: 127900
* Reduce code duplication.Owen Anderson2011-03-181-31/+13
| | | | llvm-svn: 127899
* Thumb2 PC-relative loads require a fixup rather than just an immediate.Owen Anderson2011-03-181-1/+7
| | | | llvm-svn: 127888
* The disassembler for Thumb was wrongly adding 4 to the computed imm32 offset.Johnny Chen2011-03-181-10/+2
| | | | | | Remove the offending logic and update the test cases. llvm-svn: 127843
* There are two pseudos in this case that are Thumb mode, not one.Owen Anderson2011-03-171-1/+1
| | | | llvm-svn: 127840
* It used to be that t_addrmode_s4 was used for both:Johnny Chen2011-03-171-16/+13
| | | | | | | | | | | o A8.6.195 STR (register) -- Encoding T1 o A8.6.193 STR (immediate, Thumb) -- Encoding T1 It has been changed so that now they use different addressing modes and thus different MC representation (Operand Infos). Modify the disassembler to reflect the change, and add relevant tests. llvm-svn: 127833
* Add "swi" which is an obsolete mnemonic for "svc".Nick Lewycky2011-03-171-0/+1
| | | | llvm-svn: 127788
* There were two issues fixed:Johnny Chen2011-03-151-12/+5
| | | | | | | | | | | | | | | | 1. The ARM Darwin *r9 call instructions were pseudo-ized recently. Modify the ARMDisassemblerCore.cpp file to accomodate the change. 2. The disassembler was unnecessarily adding 8 to the sign-extended imm24: imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate) // Encoding A1 It has no business doing such. Removed the offending logic. Add test cases to arm-tests.txt. llvm-svn: 127707
* The VTBL (and VTBX) instructions are rather permissive concerning the masks theyBill Wendling2011-03-151-0/+8
| | | | | | | accept. If a value in the mask is out of range, it uses the value 0, for VTBL, or leaves the value unchanged, for VTBX. llvm-svn: 127700
* Some minor cleanups based on feedback.Bill Wendling2011-03-152-8/+4
| | | | llvm-svn: 127694
* Do not form thumb2 ldrd / strd if the offset is by multiple of 4. rdar://9133587Evan Cheng2011-03-151-9/+3
| | | | llvm-svn: 127683
* Fixed an ARM disassembler bug where it does not handle STRi12 correctly ↵Johnny Chen2011-03-151-6/+9
| | | | | | | | | | because an extra register operand was erroneously added. Remove an incorrect assert which triggers the bug. rdar://problem/9131529 llvm-svn: 127642
* Clean up ARM tail calls a bit. They're pseudo-instructions for normal branches.Jim Grosbach2011-03-153-31/+71
| | | | | | | Also more cleanly separate the ARM vs. Thumb functionality. Previously, the encoding would be incorrect for some Thumb instructions (the indirect calls). llvm-svn: 127637
* Generate a VTBL instruction instead of a series of loads and stores when weBill Wendling2011-03-143-1/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | can. As Nate pointed out, VTBL isn't super performant, but it *has* to be better than this: _shuf: @ BB#0: @ %entry push {r4, r7, lr} add r7, sp, #4 sub sp, #12 mov r4, sp bic r4, r4, #7 mov sp, r4 mov r2, sp vmov d16, r0, r1 orr r0, r2, #6 orr r3, r2, #7 vst1.8 {d16[0]}, [r3] vst1.8 {d16[5]}, [r0] subs r4, r7, #4 orr r0, r2, #5 vst1.8 {d16[4]}, [r0] orr r0, r2, #4 vst1.8 {d16[4]}, [r0] orr r0, r2, #3 vst1.8 {d16[0]}, [r0] orr r0, r2, #2 vst1.8 {d16[2]}, [r0] orr r0, r2, #1 vst1.8 {d16[1]}, [r0] vst1.8 {d16[3]}, [r2] vldr.64 d16, [sp] vmov r0, r1, d16 mov sp, r4 pop {r4, r7, pc} The "illegal" testcase in vext.ll is no longer illegal. <rdar://problem/9078775> llvm-svn: 127630
* Remove some dead patterns.Jim Grosbach2011-03-144-56/+0
| | | | llvm-svn: 127601
* Indentation.Evan Cheng2011-03-141-1/+1
| | | | llvm-svn: 127595
* Sometimes isPredicable lies to us and tells us we don't need the operands.Eric Christopher2011-03-121-6/+25
| | | | | | | | | Go ahead and add them on when we might want to use them and let later passes remove them. Fixes rdar://9118569 llvm-svn: 127518
* Add FIXME.Jim Grosbach2011-03-121-0/+3
| | | | llvm-svn: 127516
* Pseudo-ize the ARM Darwin *r9 call instruction definitions. They're the sameJim Grosbach2011-03-122-27/+33
| | | | | | | | actual instruction as the non-Darwin defs, but have different call-clobber semantics and so need separate patterns. They don't need to duplicate the encoding information, however. llvm-svn: 127515
* Add a FIXME.Jim Grosbach2011-03-111-0/+2
| | | | llvm-svn: 127511
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