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* Convert ADCS and SBCS instructions into pseudos that are expanded to the ↵Owen Anderson2011-04-052-41/+56
| | | | | | ADC/ABC with the appropriate S-bit input value. llvm-svn: 128892
* Revamp the SjLj "dispatch setup" intrinsic.Bill Wendling2011-04-052-4/+4
| | | | | | | | | | | | It needed to be moved closer to the setjmp statement, because the code directly after the setjmp needs to know about values that are on the stack. Also, the 'bitcast' of the function context was causing a dead load. This wouldn't be too horrible, except that at -O0 it wasn't optimized out, and because it wasn't using the correct base pointer (if there is a VLA), it would try to access a value from a garbage address. <rdar://problem/9130540> llvm-svn: 128873
* Just use BL all the time. It's safer that way.Eric Christopher2011-04-051-9/+1
| | | | | | Fixes rdar://9184526 llvm-svn: 128869
* Fix SRS/SRSW encoding bits.Johnny Chen2011-04-051-0/+4
| | | | | | | | | rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with http://llvm.org/viewvc/llvm-project?view=rev&revision=128859. llvm-svn: 128864
* A8.6.105 MULJohnny Chen2011-04-041-1/+3
| | | | | | | | Inst{15-12} should be specified as 0b0000. rdar://problem/9231168 ARM disassembler discrepancy: erroneously accepting MUL llvm-svn: 128862
* RFE encoding should also specify the "should be" encoding bits.Johnny Chen2011-04-043-28/+49
| | | | | | | | | rdar://problem/9229922 ARM disassembler discrepancy: erroneously accepting RFE Also LDC/STC instructions are predicated while LDC2/STC2 instructions are not, fixed while doing regression testings. llvm-svn: 128859
* Fix incorrect alignment for NEON VST2b32_UPD.Johnny Chen2011-04-041-7/+132
| | | | | | rdar://problem/9225433 llvm-svn: 128841
* - Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHTBruno Cardoso Lopes2011-04-047-32/+240
| | | | | | | | | | also fix the encoding of the later. - Add a new encoding bit to describe the index mode used in AM3. - Teach printAddrMode3Operand to check by the addressing mode which index mode to print. - Testcases. llvm-svn: 128832
* Do some peephole optimizations to remove pointless VMOVs from Neon to integerCameron Zwarich2011-04-021-0/+31
| | | | | | | | registers that arise from argument shuffling with the soft float ABI. These instructions are particularly slow on Cortex A8. This fixes one half of <rdar://problem/8674845>. llvm-svn: 128759
* Fixed a bug in disassembly of STR_POST, where the immediate is the second ↵Johnny Chen2011-04-021-5/+13
| | | | | | | | | | operand in am2offset; instead of the second operand in addrmode_imm12. rdar://problem/9225289 llvm-svn: 128757
* Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000.Johnny Chen2011-04-011-0/+1
| | | | | | rdar://problem/9224276 llvm-svn: 128749
* MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is ↵Johnny Chen2011-04-011-0/+1
| | | | | | | | UNPREDICTABLE. rdar://problem/9224120 llvm-svn: 128748
* Fix the instruction table entries for AI1_adde_sube_s_irs multiclass ↵Johnny Chen2011-04-011-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | definition so that all the instruction have: let Inst{31-27} = 0b1110; // non-predicated Before, the ARM decoder was confusing: > 0x40 0xf3 0xb8 0x80 as: Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| ------------------------------------------------------------------------------------------------- adcs pc, r8, r0, asr #6 since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'. Now, the AR decoder behaves correctly: > 0x40 0xf3 0xb8 0x80 > END Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| ------------------------------------------------------------------------------------------------- adcshi pc, r8, r0, asr #6 > rdar://problem/9223094 llvm-svn: 128746
* Avoid de-referencing pass beginning of a basic block. No small test case ↵Evan Cheng2011-04-011-18/+21
| | | | | | possible. rdar://9216009 llvm-svn: 128743
* When the architecture is explicitly armv6 or thumbv6, we need to mark the ↵Owen Anderson2011-04-011-9/+15
| | | | | | object file appropriately. llvm-svn: 128739
* LDRD/STRD instructions should print both Rt and Rt2 in the asm string.Jim Grosbach2011-04-011-10/+5
| | | | llvm-svn: 128736
* Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we ↵Johnny Chen2011-04-011-0/+8
| | | | | | | | should reject the instruction as invalid. llvm-svn: 128734
* Fix LDRi12 immediate operand, which was changed to be the second operand in ↵Johnny Chen2011-04-011-3/+4
| | | | | | | | $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm). rdar://problem/9219356 llvm-svn: 128722
* Initialize HasVMLxForwarding.Benjamin Kramer2011-04-011-0/+1
| | | | llvm-svn: 128709
* Issue libcalls __udivmod*i4 / __divmod*i4 for div / rem pairs.Evan Cheng2011-04-011-0/+10
| | | | | | rdar://8911343 llvm-svn: 128696
* Remove unused variablesMatt Beaumont-Gay2011-04-011-3/+1
| | | | llvm-svn: 128692
* Apply again changes to support ARM memory asm parsing. I removedBruno Cardoso Lopes2011-03-319-76/+329
| | | | | | | | | | | | | | all LDR/STR changes and left them to a future patch. Passing all checks now. - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and fix the encoding wherever is possible. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128689
* Provide a legal pointer register class when targeting thumb1.Jakob Stoklund Olesen2011-03-312-0/+7
| | | | | | The LocalStackSlotAllocation pass was creating illegal registers. llvm-svn: 128687
* Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplierEvan Cheng2011-03-313-3/+53
| | | | | | | | | | | accumulator forwarding: vadd d3, d0, d1 vmul d3, d3, d2 => vmul d3, d0, d2 vmla d3, d1, d2 llvm-svn: 128665
* Fix single word and unsigned byte data transfer instruction encodings so thatJohnny Chen2011-03-311-0/+2
| | | | | | | | Inst{4} = 0. rdar://problem/9213022 llvm-svn: 128662
* Add BLXi to the instruction table for disassembly purpose.Johnny Chen2011-03-312-2/+23
| | | | | | | | A8.6.23 BLX (immediate) rdar://problem/9212921 llvm-svn: 128644
* Revert r128632 again, until I figure out what break the testsBruno Cardoso Lopes2011-03-319-322/+87
| | | | llvm-svn: 128635
* Reapply r128585 without generating a lib depedency cycle. An updated log:Bruno Cardoso Lopes2011-03-319-87/+322
| | | | | | | | | | | | | - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and {STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible. - Move all instructions which use am2offset without a pattern to use addrmode2. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128632
* Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and"Matt Beaumont-Gay2011-03-317-285/+66
| | | | | | This revision introduced a dependency cycle, as nlewycky mentioned by email. llvm-svn: 128597
* Somehow we managed to forget to encode the lane index for a large swathe of ↵Owen Anderson2011-03-302-21/+70
| | | | | | NEON instructions. With this fix, the entire test-suite passes with the Thumb integrated assembler. llvm-svn: 128587
* Don't try to create zero-sized stack objects.Evan Cheng2011-03-301-2/+3
| | | | llvm-svn: 128586
* - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT andBruno Cardoso Lopes2011-03-307-66/+285
| | | | | | | | | | | | | | | {STR,LDC}{2}_PRE. - Fixed the encoding in some places. - Some of those instructions were using am2offset and now use addrmode2. Codegen isn't affected, instructions which use SelectAddrMode2Offset were not touched. - Teach printAddrMode2Operand to check by the addressing mode which index mode to print. - This is a work in progress, more work to come. The idea is to change places which use am2offset to use addrmode2 instead, as to unify assembly parser. - Add testcases for assembly parser llvm-svn: 128585
* Add a ARM-specific SD node for VBSL so that forms with a constant first operandCameron Zwarich2011-03-304-9/+82
| | | | | | can be recognized. This fixes <rdar://problem/9183078>. llvm-svn: 128584
* Add intrinsics @llvm.arm.neon.vmulls and @llvm.arm.neon.vmullu.* back. FrontendsEvan Cheng2011-03-291-0/+7
| | | | | | | | | | | | | | | was lowering them to sext / uxt + mul instructions. Unfortunately the optimization passes may hoist the extensions out of the loop and separate them. When that happens, the long multiplication instructions can be broken into several scalar instructions, causing significant performance issue. Note the vmla and vmls intrinsics are not added back. Frontend will codegen them as intrinsics vmull* + add / sub. Also note the isel optimizations for catching mul + sext / zext are not changed either. First part of rdar://8832507, rdar://9203134 llvm-svn: 128502
* Add Neon SINT_TO_FP and UINT_TO_FP lowering from v4i16 to v4f32. FixesCameron Zwarich2011-03-291-0/+35
| | | | | | <rdar://problem/8875309> and <rdar://problem/9057191>. llvm-svn: 128492
* Check early if this is an unsupported opcode, so that we can avoid ↵Owen Anderson2011-03-291-0/+4
| | | | | | needlessly instantiating the base register in some cases. llvm-svn: 128481
* A8.6.188 STC, STC2Johnny Chen2011-03-291-3/+3
| | | | | | | | The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}. rdar://problem/9200661 llvm-svn: 128478
* Add safety check that didn't show up in testing.Owen Anderson2011-03-291-0/+1
| | | | llvm-svn: 128467
* Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't ↵Owen Anderson2011-03-296-77/+21
| | | | | | actually exist. llvm-svn: 128461
* Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during ↵Evan Cheng2011-03-291-15/+81
| | | | | | | | | | | | | | | | | | | isel lowering to fold the zero-extend's and take advantage of no-stall back to back vmul + vmla: vmull q0, d4, d6 vmlal q0, d5, d6 is faster than vaddl q0, d4, d5 vmovl q1, d6 vmul q0, q0, q1 This allows us to vmull + vmlal for: f = vmull_u8( vget_high_u8(s), c); f = vmlal_u8(f, vget_low_u8(s), c); rdar://9197392 llvm-svn: 128444
* Fix ARM disassembly for PLD/PLDW/PLI which suffers from code rot and add ↵Johnny Chen2011-03-282-5/+18
| | | | | | | | some test cases. Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly. llvm-svn: 128417
* Fixed the t2PLD and friends disassembly and add two test cases.Johnny Chen2011-03-262-10/+39
| | | | llvm-svn: 128322
* Fix the bfi handling for or (and a mask) (and b mask). We need the twoEric Christopher2011-03-261-9/+10
| | | | | | | | | | | | | | masks to match inversely for the code as is to work. For the example given we actually want: bfi r0, r2, #1, #1 not #0, however, given the way the pattern is written it's not possible at the moment. Fixes rdar://9177502 llvm-svn: 128320
* Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode ↵Johnny Chen2011-03-251-6/+6
| | | | | | | | | | GPRRegClassID. Also add some test cases. rdar://problem/9189829 llvm-svn: 128304
* DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to ↵Johnny Chen2011-03-251-2/+3
| | | | | | | | RegClass. Add two test cases. rdar://problem/9182892 llvm-svn: 128299
* Modify DisassembleThumb2LdStEx() to be more robust/correct in light of ↵Johnny Chen2011-03-251-6/+6
| | | | | | | | recent change to t2LDREX/t2STREX instructions. Add two test cases. llvm-svn: 128293
* Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. ↵Johnny Chen2011-03-251-0/+5
| | | | | | | | Modify the disassembler to handle that. rdar://problem/9184053 llvm-svn: 128285
* Also need to handle invalid imod values for CPS2p.Johnny Chen2011-03-251-4/+11
| | | | | | rdar://problem/9186136 llvm-svn: 128283
* Ignore special ARM allocation hints for unexpected register classes.Jakob Stoklund Olesen2011-03-251-0/+4
| | | | | | | | | Add an assertion to linear scan to prevent it from allocating registers outside the register class. <rdar://problem/9183021> llvm-svn: 128254
* Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the ↵Johnny Chen2011-03-251-9/+9
| | | | | | | | register classes were changed), modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1. llvm-svn: 128252
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