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* Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified.Jason W Kim2010-11-082-10/+78
| | | | llvm-svn: 118422
* Complete listing of ARM/MC/ELF relocation enumsJason W Kim2010-11-081-3/+134
| | | | llvm-svn: 118413
* Make RegList an ASM operand so that TableGen will generate code for it. This isBill Wendling2010-11-081-2/+7
| | | | | | an initial implementation and may change once reglists are fully fleshed out. llvm-svn: 118390
* Revert.Bill Wendling2010-11-081-1/+1
| | | | llvm-svn: 118389
* In this context, a reglist is a reg.Bill Wendling2010-11-071-1/+1
| | | | llvm-svn: 118375
* Add support for parsing register lists. We can't use a bitfield to keep track ofBill Wendling2010-11-061-22/+64
| | | | | | | | | | | the registers, because the register numbers may be much greater than the number of bits available in the machine's register. I extracted the register list verification code out of the actual parsing of the registers. This made checking for errors much easier. It also limits the number of warnings that would be emitted for cascading infractions. llvm-svn: 118363
* Return the base register of a register list for the "getReg()" method. This isBill Wendling2010-11-061-3/+8
| | | | | | | to satisfy the ClassifyOperand method of the Asm matcher without having to add a RegList type to every back-end. llvm-svn: 118360
* General cleanup:Bill Wendling2010-11-061-36/+21
| | | | | | | - Make ARMOperand a class so that some things are internal to the class. - Reformatting. llvm-svn: 118357
* Add a RegList (register list) object to ARMOperand. It will be used soon to holdBill Wendling2010-11-061-1/+38
| | | | | | | (surprise!) a list of registers. Register lists are consecutive, so we only need to record the start register plus the number of registers. llvm-svn: 118351
* Fix grammar.Bill Wendling2010-11-061-1/+1
| | | | llvm-svn: 118341
* Fix grammar.Bill Wendling2010-11-061-3/+3
| | | | llvm-svn: 118340
* MatchRegisterName() returns 0 if it can't match the register.Bill Wendling2010-11-061-2/+2
| | | | llvm-svn: 118339
* Use TryParseRegister() instead of MatchRegisterName(). The former returns -1Bill Wendling2010-11-061-5/+2
| | | | | | while the latter doesn't. llvm-svn: 118338
* Make sure we have movw on the target before using it.Eric Christopher2010-11-061-1/+1
| | | | | | Fixes 8559. llvm-svn: 118333
* Hook up the '.code {16|32}' directive to the streamer.Jim Grosbach2010-11-051-2/+5
| | | | llvm-svn: 118310
* Hook up the '.thumb_func' directive to the streamer.Jim Grosbach2010-11-051-3/+5
| | | | llvm-svn: 118307
* Fix past-o.Jim Grosbach2010-11-051-1/+1
| | | | llvm-svn: 118304
* MC'ize the '.code 16' and '.thumb_func' ARM directives.Jim Grosbach2010-11-051-11/+2
| | | | llvm-svn: 118301
* Disallow the certain NEON modified-immediate forms when generating vorr or vbic.Owen Anderson2010-11-052-7/+21
| | | | llvm-svn: 118300
* MC'ize simple ARMConstantValue entry emission (with a FIXME).Jim Grosbach2010-11-051-28/+37
| | | | llvm-svn: 118295
* Add codegen and encoding support for the immediate form of vbic.Owen Anderson2010-11-053-6/+78
| | | | llvm-svn: 118291
* Enable MachO writing for ARM/Darwin. Lots of stuff still doesn't workJim Grosbach2010-11-051-1/+0
| | | | | | (relocations, e.g.), but this will allow simple things to flow through. llvm-svn: 118289
* Allow targets to specify the MachO CPUType/CPUSubtype information.Jim Grosbach2010-11-051-1/+4
| | | | llvm-svn: 118288
* Add FIXME.Jim Grosbach2010-11-051-0/+1
| | | | llvm-svn: 118280
* In the calling convention logic, ValVT is always a legal type,Duncan Sands2010-11-042-8/+8
| | | | | | | and as such can be represented by an MVT - the more complicated EVT is not needed. Use MVT for ValVT everywhere. llvm-svn: 118245
* Fix @llvm.prefetch isel. Selecting between pld / pldw using the first ↵Evan Cheng2010-11-043-38/+37
| | | | | | immediate rw. There is currently no intrinsic that matches to pli. llvm-svn: 118237
* Add ARM fixup info for load/store label references. Probably will need a bit ofJim Grosbach2010-11-042-30/+79
| | | | | | | tweaking when we start using it for object file emission or JIT, but it's a start. llvm-svn: 118221
* Add encoding for VSTR.Bill Wendling2010-11-042-30/+30
| | | | llvm-svn: 118220
* Teach ARM Target to use the tblgen support for generating an MC'izedJim Grosbach2010-11-033-47/+64
| | | | | | CodeEmitter. llvm-svn: 118209
* Covert VORRIMM to be produced via early target-specific DAG combining, ↵Owen Anderson2010-11-031-31/+26
| | | | | | | | rather than legalization. This is both the conceptually correct place for it, as well as allowing it to be more aggressive. llvm-svn: 118204
* Add support for code generation of the one register with immediate form of vorr.Owen Anderson2010-11-033-1/+74
| | | | | | | We could be more aggressive about making this work for a larger range of constants, but this seems like a good start. llvm-svn: 118201
* trailing whitespaceJim Grosbach2010-11-031-2/+2
| | | | llvm-svn: 118199
* Optimize generated code for integer materialization a bit.Eric Christopher2010-11-031-1/+13
| | | | llvm-svn: 118192
* Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by ↵Owen Anderson2010-11-031-9/+31
| | | | | | | | | element size. Instead, all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with the immediate shifted left to reflect the increased element size. llvm-svn: 118183
* Add codegen patterns for VST1-lane instructions. Radar 8599955.Bob Wilson2010-11-031-8/+17
| | | | llvm-svn: 118176
* Check for extractelement with a variable operand for the element number.Bob Wilson2010-11-031-10/+15
| | | | | | For NEON we had been assuming this was always an immediate constant. llvm-svn: 118175
* Simplify uses of MVT and EVT. An MVT can be compared directlyDuncan Sands2010-11-033-11/+9
| | | | | | | with a SimpleValueType, while an EVT supports equality and inequality comparisons with SimpleValueType. llvm-svn: 118169
* Inside the calling convention logic LocVT is always a simpleDuncan Sands2010-11-032-43/+43
| | | | | | | | | | value type, so there is no point in passing it around using an EVT. Use the simpler MVT everywhere. Rather than trying to propagate this information maximally in all the code that using the calling convention stuff, I chose to do a mainly low impact change instead. llvm-svn: 118167
* Fix preload instruction isel. Only v7 supports pli, and only v7 with mp ↵Evan Cheng2010-11-0310-36/+83
| | | | | | extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. llvm-svn: 118160
* Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.Evan Cheng2010-11-035-47/+47
| | | | llvm-svn: 118152
* Put the PC encoding in the correct bit position.Bill Wendling2010-11-031-1/+1
| | | | llvm-svn: 118151
* Invert these branches by default, it makes assembly comparisons a littleEric Christopher2010-11-031-2/+2
| | | | | | easier to read. llvm-svn: 118148
* The MC code couldn't handle ARM LDR instructions with negative offsets:Bill Wendling2010-11-036-52/+140
| | | | | | | | | | | | vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. llvm-svn: 118144
* Remove unused function.Jim Grosbach2010-11-032-9/+0
| | | | llvm-svn: 118141
* Remove the no longer used 'Modifier' optional operand to the ARMJim Grosbach2010-11-032-17/+8
| | | | | | printOperand() asm printer helper functions. rdar://8425198 llvm-svn: 118140
* Remove unused function.Jim Grosbach2010-11-032-12/+0
| | | | llvm-svn: 118139
* Break ARM addrmode4 (load/store multiple base address) into its constituentJim Grosbach2010-11-039-104/+90
| | | | | | | parts. Represent the operation mode as an optional operand instead. rdar://8614429 llvm-svn: 118137
* Two sets of changes. Sorry they are intermingled.Evan Cheng2010-11-034-78/+77
| | | | | | | | | | | | | 1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to "optimize for latency". Call instructions don't have the right latency and this is more likely to use introduce spills. 2. Fix if-converter cost function. For ARM, it should use instruction latencies, not # of micro-ops since multi-latency instructions is completely executed even when the predicate is false. Also, some instruction will be "slower" when they are predicated due to the register def becoming implicit input. rdar://8598427 llvm-svn: 118135
* Modify scheduling itineraries to correct instruction latencies (not operandEvan Cheng2010-11-032-314/+314
| | | | | | latencies) of loads. llvm-svn: 118134
* Make sure we're only storing a single bit here.Eric Christopher2010-11-021-2/+9
| | | | llvm-svn: 118126
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