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* [arm-fast-isel] Add support for non-global callee.Chad Rosier2012-05-231-7/+17
| | | | | | Patch by Jush Lu <jush.msn@gmail.com>. llvm-svn: 157336
* ARMDisassembler.cpp: Fix utf8 char in comments.NAKAMURA Takumi2012-05-221-3/+3
| | | | llvm-svn: 157292
* ARM: .end_data_region mismatch in Thumb2.Jim Grosbach2012-05-211-2/+5
| | | | | | | | | | 32-bit offset jump tables just use real branch instructions and so aren't marked as data regions. We were still emitting the .end_data_region marker though, which assert()ed. rdar://11499158 llvm-svn: 157221
* Thumb2: RSB source register should be rGRP not GPRnopc.Jim Grosbach2012-05-211-4/+4
| | | | | | t2RSB defined the operand correctly, but tRSBS didn't. llvm-svn: 157200
* Use the right register class for LDRrs.Jakob Stoklund Olesen2012-05-201-1/+1
| | | | llvm-svn: 157152
* Transfer memory operands to the right instruction.Jakob Stoklund Olesen2012-05-201-1/+1
| | | | | | They need to go on the PICLDR as the verifier points out. llvm-svn: 157151
* Refactor data-in-code annotations.Jim Grosbach2012-05-183-22/+40
| | | | | | | | | | | | | | | | | | | | | | Use a dedicated MachO load command to annotate data-in-code regions. This is the same format the linker produces for final executable images, allowing consistency of representation and use of introspection tools for both object and executable files. Data-in-code regions are annotated via ".data_region"/".end_data_region" directive pairs, with an optional region type. data_region_directive := ".data_region" { region_type } region_type := "jt8" | "jt16" | "jt32" | "jta32" end_data_region_directive := ".end_data_region" The previous handling of ARM-style "$d.*" labels was broken and has been removed. Specifically, it didn't handle ARM vs. Thumb mode when marking the end of the section. rdar://11459456 llvm-svn: 157062
* Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missingKevin Enderby2012-05-173-11/+54
| | | | | | | | | | the 0b10 mask encoding bits. Make MSR APSR writes without a _<bits> qualifier an alias for MSR APSR_nzcvq even though ARM as deprecated it use. Also add support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions. Some FIXMEs in the code for better error checking when versions shouldn't be used. rdar://11457025 llvm-svn: 157019
* Remove incorrect pattern for ARM SMML instruction.Tim Northover2012-05-171-2/+1
| | | | | | Patch by Meador Inge. llvm-svn: 156989
* Allow MCCodeEmitter access to the target MCRegisterInfo.Jim Grosbach2012-05-152-0/+3
| | | | | | | | Add the MCRegisterInfo to the factories and constructors. Patch by Tom Stellard <Tom.Stellard@amd.com>. llvm-svn: 156828
* Fix use of uninitialized variable.David Blaikie2012-05-141-1/+1
| | | | | | Found by GCC's maybe-uninitialized. llvm-svn: 156780
* [fast-isel] Add support for selecting @llvm.trap().Chad Rosier2012-05-111-0/+4
| | | | llvm-svn: 156646
* [fast-isel] Remove -disable-arm-fast-isel option. -fast-isel=0 suffices. ↵Chad Rosier2012-05-111-12/+2
| | | | | | Minor cleanup. llvm-svn: 156632
* [fast-isel] Cleaner fix for when we're unable to handle a non-double multi-regChad Rosier2012-05-111-4/+21
| | | | | | | | retval. Hoists check before emitting the call to avoid unnecessary work. rdar://11430407 PR12796 llvm-svn: 156628
* [fast-isel] Rather then assert (or segfault in a non-asserts build), fall backChad Rosier2012-05-111-2/+4
| | | | | | | | to selection DAG isel if we're unable to handle a non-double multi-reg retval. rdar://11430407 PR12796 llvm-svn: 156622
* The return type is an unsigned, not a bool.Chad Rosier2012-05-111-1/+1
| | | | llvm-svn: 156621
* Add space before an open parenthesis in control flow statements.Manman Ren2012-05-111-2/+2
| | | | llvm-svn: 156620
* Added the missing bit definition for the 4th bit of the STR (post reg) ↵Silviu Baranga2012-05-112-0/+5
| | | | | | instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions. llvm-svn: 156609
* Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate ↵Silviu Baranga2012-05-112-3/+9
| | | | | | offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate. llvm-svn: 156608
* ARM: peephole optimization to remove cmp instructionManman Ren2012-05-111-27/+119
| | | | | | | | | | | | | | | | | This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 llvm-svn: 156599
* Revert: 156550 "ARM: peephole optimization to remove cmp instruction"Manman Ren2012-05-101-118/+27
| | | | | | This commit broke an external linux bot and gave a compile-time warning. llvm-svn: 156556
* ARM: peephole optimization to remove cmp instructionManman Ren2012-05-101-27/+118
| | | | | | | | | | | | | | | | | This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 llvm-svn: 156550
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-076-7/+14
| | | | | | | | | | | | | The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! llvm-svn: 156328
* Nuke a few dead remnants of the CBE.Jim Grosbach2012-05-051-27/+0
| | | | llvm-svn: 156241
* Add a new target hook "predictableSelectIsExpensive".Benjamin Kramer2012-05-051-0/+3
| | | | | | | | | | | This will be used to determine whether it's profitable to turn a select into a branch when the branch is likely to be predicted. Currently enabled for everything but Atom on X86 and Cortex-A9 devices on ARM. I'm not entirely happy with the name of this flag, suggestions welcome ;) llvm-svn: 156233
* Tweak to the fix in r156212, as with the change in removing the shift theKevin Enderby2012-05-041-1/+1
| | | | | | SignExtend32<22>(Val<<1) also needs to change to SignExtend32<21>(Val) . llvm-svn: 156213
* Fix a bug in the ARM disassembler for wide branch conditional instructionsKevin Enderby2012-05-041-1/+1
| | | | | | | where the symbolic operand's displacement was incorrectly shifted left by 1. rdar://11387046 llvm-svn: 156212
* Added missing CMN case in Thumb2SizeReduction pass so that LLVM emits ↵Sebastian Pop2012-05-041-0/+1
| | | | | | 16-bits encoding of CMN instructions. llvm-svn: 156195
* Pacify GCC's -Wreturn-typeMatt Beaumont-Gay2012-05-041-0/+1
| | | | llvm-svn: 156189
* Make ARM and Mips use TargetMachine::getTLSModel()Hans Wennborg2012-05-042-9/+17
| | | | | | | | This moves the logic for selecting a TLS model to a single place, instead of the previous three (ARM, Mips, and X86 which already uses this function). llvm-svn: 156162
* Remove the SubRegClasses field from RegisterClass descriptions.Jakob Stoklund Olesen2012-05-041-20/+4
| | | | | | This information in now computed by TableGen. llvm-svn: 156152
* Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bitsKevin Enderby2012-05-033-42/+99
| | | | | | | | | for the assembler and disassembler. Which were not being set/read correctly for offsets greater than 22 bits in some cases. Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles! llvm-svn: 156118
* Fixed disassembler for vstm/vldm ARM VFP instructions.Silviu Baranga2012-05-031-4/+6
| | | | llvm-svn: 156077
* ARM: Add missing two-operand VBIC aliases.Jim Grosbach2012-05-021-0/+2
| | | | llvm-svn: 156019
* Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures.Richard Barton2012-05-021-4/+8
| | | | llvm-svn: 155983
* ARM: Add a few missing add->sub aliases w/ 'w' suffix.Jim Grosbach2012-05-011-0/+11
| | | | | | | | | | | | | | Aliases for adding a negative immediate when using an explicit 'w' suffix. E.g., adds.w r2, #-16 adds.w r2, r2, #-16 addw r2, #-16 addw r2, #-16 addw r2, r2, #-16 rdar://11330769 llvm-svn: 155946
* ARM: allow vanilla expressions for movw/movt.Jim Grosbach2012-05-011-4/+16
| | | | | | | | | | Expressions for movw/movt don't always have an :upper16: or :lower16: on them and that's ok. When they don't, it's just a plain [0-65536] immediate result, effectively the same as a :lower16: variant kind. rdar://10550147 llvm-svn: 155941
* Change the PassManager from a reference to a pointer.Bill Wendling2012-05-011-10/+10
| | | | | | | | | The TargetPassManager's default constructor wants to initialize the PassManager to 'null'. But it's illegal to bind a null reference to a null l-value. Make the ivar a pointer instead. PR12468 llvm-svn: 155902
* ARM: Diagnostics for out of range fixups.Jim Grosbach2012-04-301-34/+52
| | | | | | | | | | | Replace some assert() calls w/ actual diagnostics. In a perfect world, there'd be range checks on these values long before things ever reached this code. For now, though, issuing a better-late-than-never diagnostic is still a big improvement over assert(). rdar://11347287 llvm-svn: 155851
* Fix address calculation error from r155744.Jakob Stoklund Olesen2012-04-301-1/+6
| | | | | | | | | | | | This was exposed by SingleSource/UnitTests/Vector/constpool.c. The computed size of a basic block isn't always a multiple of its known alignment, and that can introduce extra alignment padding after the block. <rdar://problem/11347135> llvm-svn: 155845
* Don't introduce illegal types when creating vmull operations. <rdar://11324364>Bob Wilson2012-04-301-1/+3
| | | | | | | | ARM BUILD_VECTORs created after type legalization cannot use i8 or i16 operands, since those types are not legal. Instead use i32 operands, which will be implicitly truncated by the BUILD_VECTOR to match the element type. llvm-svn: 155824
* Fix a problem with blocks that need to be split twice.Jakob Stoklund Olesen2012-04-281-3/+5
| | | | | | | | | The code could search past the end of the basic block when there was already a constant pool entry after the block. Test case with giant basic block in SingleSource/UnitTests/Vector/constpool.c llvm-svn: 155753
* ARM: Thumb add(sp plus register) asm constraints.Jim Grosbach2012-04-272-2/+22
| | | | | | | | | | Make sure when parsing the Thumb1 sp+register ADD instruction that the source and destination operands match. In thumb2, just use the wide encoding if they don't. In Thumb1, issue a diagnostic. rdar://11219154 llvm-svn: 155748
* ARM: Tweak tADDrSP definition for consistent operand order.Jim Grosbach2012-04-272-3/+3
| | | | | | Make the operand order of the instruction match that of the asm syntax. llvm-svn: 155747
* Track worst case alignment padding more accurately.Jakob Stoklund Olesen2012-04-271-42/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, ARMConstantIslandPass would conservatively compute the address of an aligned basic block as: RoundUpToAlignment(Offset + UnknownPadding) This worked fine for the layout algorithm itself, but it could fool the verify() function because it accounts for alignment padding twice: Once when adding the worst case UnknownPadding, and again by rounding up the fictional block offset. This meant that when optimizeThumb2Instructions would shrink an instruction, the conservative distance estimate could grow. That shouldn't be possible since the woorst case alignment padding wss already included. This patch drops the use of RoundUpToAlignment, and depends only on worst case padding to compute conservative block offsets. This has the weird effect that the computed offset for an aligned block may not be aligned. The important difference is that shrinking an instruction can never cause the estimated distance between two instructions to grow. The estimated distance is always larger than the real distance that only the assembler knows. <rdar://problem/11339352> llvm-svn: 155744
* Fix the order of the operands in the llvm.fma intrinsic patterns for ARM,Lang Hames2012-04-272-24/+25
| | | | | | <rdar://problem/11325085>. llvm-svn: 155724
* Fix ARM assembly parsing for upper case condition codes on IT instructions.Richard Barton2012-04-271-1/+1
| | | | llvm-svn: 155720
* Refactor IT handling not to store the bottom bit of the condition code in ↵Richard Barton2012-04-273-14/+7
| | | | | | the mask operand in the MCInst. llvm-svn: 155700
* Implement a bastardized ABI.Evan Cheng2012-04-272-3/+5
| | | | llvm-svn: 155686
* - thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2Evan Cheng2012-04-272-16/+28
| | | | | | | | instructions. - However, it does support dmb, dsb, isb, mrs, and msr. rdar://11331541 llvm-svn: 155685
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