summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM
Commit message (Collapse)AuthorAgeFilesLines
...
* Disable sibcall optimization for Thumb1 for now since ↵Evan Cheng2010-06-191-8/+17
| | | | | | Thumb1RegisterInfo::emitEpilogue is not expecting them. llvm-svn: 106368
* Indentation and remove dead code.Evan Cheng2010-06-191-58/+44
| | | | llvm-svn: 106362
* Silence compiler warnings.Dan Gohman2010-06-191-3/+3
| | | | llvm-svn: 106360
* Move ARM if-conversion before post-ra scheduling.Evan Cheng2010-06-181-15/+2
| | | | llvm-svn: 106355
* Update cmake list.Evan Cheng2010-06-181-0/+1
| | | | llvm-svn: 106348
* Thumb2 hazard recognizer.Evan Cheng2010-06-182-0/+90
| | | | llvm-svn: 106347
* Allow ARM if-converter to be run after post allocation scheduling.Evan Cheng2010-06-189-35/+215
| | | | | | | | | | | | | | | | - This fixed a number of bugs in if-converter, tail merging, and post-allocation scheduler. If-converter now runs branch folding / tail merging first to maximize if-conversion opportunities. - Also changed the t2IT instruction slightly. It now defines the ITSTATE register which is read by instructions in the IT block. - Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't change the instruction ordering in the IT block (since IT mask has been finalized). It also ensures no other instructions can be scheduled between instructions in the IT block. This is not yet enabled. llvm-svn: 106344
* back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set)Jim Grosbach2010-06-181-0/+4
| | | | llvm-svn: 106342
* Enable Expand handling of atomics for subtargets that can't do them inline.Jim Grosbach2010-06-181-3/+39
| | | | llvm-svn: 106336
* Rewrite chained if's as switches and replace assertions with llvm_unreachableBob Wilson2010-06-181-35/+55
| | | | | | (as suggested in radar 8104405). llvm-svn: 106318
* Fix ARM/Thumb reversal in previous attempt.Dale Johannesen2010-06-181-2/+2
| | | | llvm-svn: 106314
* When using ADDri to get the address of a stack object, 255 is a conservativeJakob Stoklund Olesen2010-06-181-0/+9
| | | | | | | limit on the offset that can be materialized without using the register scavenger. llvm-svn: 106312
* An attempt to fix the problem Anton reported withDale Johannesen2010-06-182-2/+7
| | | | | | | ARM tail calls. Don't know if it works, but it doesn't break Darwin. llvm-svn: 106309
* Enable tail calls on ARM by default, with someDale Johannesen2010-06-181-1/+1
| | | | | | | | | | | | | | basic tests. This has been well tested on Darwin but not elsewhere. It should work provided the linker correctly resolves B.W <label in other function> which it has not seen before, at least from llvm-based compilers. I'm leaving the arm-tail-calls switch in until I see if there's any problems because of that; it might need to be disabled for some environments. llvm-svn: 106299
* Start TargetRegisterClass indices at 0 instead of 1, so thatDan Gohman2010-06-182-41/+43
| | | | | | | MachineRegisterInfo doesn't have to confusingly allocate an extra entry. llvm-svn: 106296
* Last round of changes for ARM tail calls.Dale Johannesen2010-06-182-9/+16
| | | | | | Not turning them on yet. llvm-svn: 106295
* Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86Jakob Stoklund Olesen2010-06-181-1/+1
| | | | | | | does for {flags}. If we create virtual registers of the CCR class, RegAllocFast may try to spill them, and we can't do that. llvm-svn: 106289
* Eliminate unnecessary uses of getZExtValue().Dan Gohman2010-06-181-1/+1
| | | | llvm-svn: 106279
* Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). ThisStuart Hastings2010-06-172-10/+9
| | | | | | | | | | | | addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. llvm-svn: 106243
* Thumb1 and any pre-v6 ARM target should use the libcall expansion ofJim Grosbach2010-06-171-1/+6
| | | | | | ISD::MEMBARRIER. v7 and v7 ARM mode continue to use the custom lowering. llvm-svn: 106204
* simplify code a bit and add a more explanatory assert for cases thatJim Grosbach2010-06-171-15/+11
| | | | | | previously would result in 'cannot yet select' errors. llvm-svn: 106199
* format and 80-column cleanupJim Grosbach2010-06-161-5/+4
| | | | llvm-svn: 106173
* Don't attempt preserving conservative kill flags. We were doing it wrong.Jakob Stoklund Olesen2010-06-161-2/+1
| | | | | | This is before LiveVariables anyway, where these kill flags are recalculated. llvm-svn: 106157
* Remove the hidden "neon-reg-sequence" option. The reg sequences are workingBob Wilson2010-06-164-272/+157
| | | | | | now, so there's no need to disable them. llvm-svn: 106155
* Make post-ra scheduling, anti-dep breaking, and register scavenger ↵Evan Cheng2010-06-162-3/+17
| | | | | | (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. llvm-svn: 106091
* Add file missing from previous commit.Dale Johannesen2010-06-151-6/+14
| | | | llvm-svn: 106058
* Next round of tail call changes. Register used in a tailDale Johannesen2010-06-156-22/+107
| | | | | | | | call must not be callee-saved; following x86, add a new regclass to represent this. Also fixes a couple of bugs. Still disabled by default; Thumb doesn't work yet. llvm-svn: 106053
* Add basic support for NEON modified immediates besides VMOV.Bob Wilson2010-06-153-13/+25
| | | | llvm-svn: 106030
* Add <cstddef> include to get ptrdiff_t, for gcc-4.6; patch by Dimitry Andric.Daniel Dunbar2010-06-151-0/+1
| | | | llvm-svn: 105994
* VMOVQQ and VMOVQQQQ are pseudo instructions and not predicable.Bob Wilson2010-06-151-1/+4
| | | | llvm-svn: 105990
* Make sure to skip dbg_value instructions when finding an insertion point forJim Grosbach2010-06-151-1/+2
| | | | | | the combined load/store instruction. rdar://7797940 llvm-svn: 105982
* Rename functions referring to VMOV immediates to refer to NEON "modifiedBob Wilson2010-06-143-30/+34
| | | | | | | | immediate" operands. These functions have so far only been used for VMOV but they also apply to other NEON instructions with modified immediate operands. No functional changes. llvm-svn: 105969
* Add a missing bitcast. This code used to only handle conversions betweenBob Wilson2010-06-111-1/+2
| | | | | | | i64 and f64 types, but now it also handle Neon vector types, so the f64 result of VMOVDRR may need to be converted to a Neon type. Radar 8084742. llvm-svn: 105845
* Add instruction encoding for the Neon VMOV immediate instruction. This changesBob Wilson2010-06-118-121/+221
| | | | | | | | | | | the machine instruction representation of the immediate value to be encoded into an integer with similar fields as the actual VMOV instruction. This makes things easier for the disassembler, since it can just stuff the bits into the immediate operand, but harder for the asm printer since it has to decode the value to be printed. Testcase for the encoding will follow later when MC has more support for ARM. llvm-svn: 105836
* Delete code that's not safe.Evan Cheng2010-06-101-13/+0
| | | | llvm-svn: 105774
* be slightly more subtle about skipping dbg_value instructions; otherwise, if aJim Grosbach2010-06-091-5/+6
| | | | | | | | dbg_value immediately follows a sequence of ldr/str instructions that should be combined into an ldm/stm and is the last instruction in the block, then combine may end up being skipped. llvm-svn: 105758
* Allow target to place 2-address pass inserted copies in better spots. Thumb2 ↵Evan Cheng2010-06-093-12/+52
| | | | | | will use this to try to avoid breaking up IT blocks. llvm-svn: 105745
* Typo.Evan Cheng2010-06-091-1/+1
| | | | llvm-svn: 105677
* Thumb2 IT blocks are fairly expensive. When there are multiple selects usingEvan Cheng2010-06-093-13/+292
| | | | | | | | | | | | | | | the same condition, it's important to make sure they are scheduled together to avoid forming multiple IT blocks. I'm adding a pre-regalloc pass that forms IT blocks early (by re-scheduling instructions and split basic blocks) to attempt to fix this. This is not turned on by default since I am not sure this is the right fix. Another issue is llvm selects are modeled as two-address conditional moves. This can be very bad when the copies before the conditional moves are not coalesced away. Teach IT formation pass to move the copies above the IT block (when legal) to avoid breaking the IT block. llvm-svn: 105669
* fix copy/paste/modify think-oJim Grosbach2010-06-081-1/+1
| | | | llvm-svn: 105653
* Reapply r105521, this time appending "LLU" to 64 bitBruno Cardoso Lopes2010-06-082-6/+6
| | | | | | immediates to avoid breaking the build. llvm-svn: 105652
* fix typoJim Grosbach2010-06-081-1/+1
| | | | llvm-svn: 105634
* Fix up a comment.Bob Wilson2010-06-081-2/+2
| | | | llvm-svn: 105591
* Further changes for Neon vector shuffles:Bob Wilson2010-06-072-68/+56
| | | | | | | | | | - change isShuffleMaskLegal to show that all shuffles with 32-bit and 64-bit elements are legal - the Neon shuffle instructions do not support 64-bit elements, but we were not checking for that before lowering shuffles to use them - remove some 64-bit element vduplane patterns that are no longer needed llvm-svn: 105586
* Handle dbg_value instructions (i.e., skip them) when generating IT blocks.Jim Grosbach2010-06-071-3/+4
| | | | | | rdar://7797940 llvm-svn: 105557
* revert r105521, which is breaking the buildbots with stuff like this:Chris Lattner2010-06-052-6/+6
| | | | | | | | | | | | | | In file included from X86InstrInfo.cpp:16: X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type llvm-svn: 105524
* Initial AVX support for some instructions. No patterns matchedBruno Cardoso Lopes2010-06-052-6/+6
| | | | | | yet, only assembly encoding support. llvm-svn: 105521
* Improvements to tail call code. No functional effectDale Johannesen2010-06-051-20/+22
| | | | | | unless using -arm-tail-calls. llvm-svn: 105515
* More thoroughly disable tails calls by default.Dale Johannesen2010-06-041-3/+3
| | | | | | 8060143, although this doesn't fix the real problem with tail call. llvm-svn: 105472
* Another fix to prevent debug info from affecting codegen. rdar://7797940Jim Grosbach2010-06-041-0/+4
| | | | llvm-svn: 105470
OpenPOWER on IntegriCloud