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* First steps in ARM AsmParser support for .eabi_attribute and .archJason W Kim2011-12-201-0/+18
| | | | | | | (Both used for Linux gnueabi) No behavioral change yet (no tests need so far) llvm-svn: 146977
* Fix up the CMake build for the new files added in r146960, they'reChandler Carruth2011-12-201-0/+1
| | | | | | likely to stay either way that discussion ends up resolving itself. llvm-svn: 146966
* Unweaken vtables as per ↵David Blaikie2011-12-208-2/+35
| | | | | | http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
* Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930.Bob Wilson2011-12-201-2/+5
| | | | | | | | | | | | We used to rely on the *eh_sjlj_setjmp instructions to mark that a function with setjmp/longjmp exception handling clobbers all the registers. But with the recent reorganization of ARM EH, those eh_sjlj_setjmp instructions are expanded away earlier, before PEI can see them to determine what registers to save and restore. Mark the dispatchsetup instruction in the same way, since that instruction cannot be expanded early. This also more accurately reflects when the registers are clobbered. llvm-svn: 146949
* ARM assembly shifts by zero should be plain 'mov' instructions.Jim Grosbach2011-12-201-0/+17
| | | | | | | | | | "mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's not strictly legal UAL syntax. It's a common extension and the friendly thing to do. rdar://10604663 llvm-svn: 146937
* ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates.Jim Grosbach2011-12-192-0/+45
| | | | | | | | e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117" rdar://10603913 llvm-svn: 146925
* ARM assembly parsing and encoding support for LDRD(label).Jim Grosbach2011-12-195-3/+72
| | | | | | rdar://9932658 llvm-svn: 146921
* ARM NEON two-operand aliases for VPADD.Jim Grosbach2011-12-191-0/+10
| | | | | | rdar://10602276 llvm-svn: 146895
* ARM VFP pre-UAL mnemonic aliases for fmul[sd].Jim Grosbach2011-12-192-1/+4
| | | | llvm-svn: 146892
* ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd].Jim Grosbach2011-12-192-1/+5
| | | | llvm-svn: 146887
* ARM NEON implied destination aliases for VMAX/VMIN.Jim Grosbach2011-12-191-0/+62
| | | | llvm-svn: 146885
* ARM NEON relax parse time diagnostics for alignment specifiers.Jim Grosbach2011-12-193-9/+11
| | | | | | | There's more variation that we need to handle. Error checking will need to be on operand predicates. llvm-svn: 146884
* Tidy up.Jim Grosbach2011-12-191-7/+7
| | | | llvm-svn: 146882
* Remove a register class that can just as well be synthesized.Jakob Stoklund Olesen2011-12-191-8/+0
| | | | | | | Add the new TableGen register class synthesizer feature to the release notes. llvm-svn: 146875
* Emit a getMatchingSuperRegClass() implementation for every target.Jakob Stoklund Olesen2011-12-192-105/+0
| | | | | | | | | Use information computed while inferring new register classes to emit accurate, table-driven implementations of getMatchingSuperRegClass(). Delete the old manual, error-prone implementations in the targets. llvm-svn: 146873
* Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle.Evan Cheng2011-12-171-4/+7
| | | | llvm-svn: 146805
* Preserve more memory operands in ARMExpandPseudo.Jakob Stoklund Olesen2011-12-171-0/+4
| | | | | | I don't think this affects anything but verbose assembly. llvm-svn: 146787
* Fix off-by-one error in bucket sort.Jakob Stoklund Olesen2011-12-161-1/+1
| | | | | | | | | The bad sorting caused a misaligned basic block when building 176.vpr in ARM mode. <rdar://problem/10594653> llvm-svn: 146767
* Don't adjust for alignment padding in OffsetIsInRange.Jakob Stoklund Olesen2011-12-161-16/+1
| | | | | | | | | | | This adjustment is already included in the block offsets computed by BasicBlockInfo, and adjusting again here can cause the pass to loop. When CreateNewWater splits a basic block, OffsetIsInRange would reject the new CPE on the next pass because of the too conservative alignment adjustment. This caused the block to be split again, and so on. llvm-svn: 146751
* Note ARM constant island alignment in the release notes.Jakob Stoklund Olesen2011-12-161-0/+1
| | | | | | | | The command line option should be removed, but not until the feature has gotten a lot of testing. The ARMConstantIslandPass tends to have subtle bugs that only show up after a while. llvm-svn: 146739
* ARM NEON aliases for vmovq.f*Jim Grosbach2011-12-161-0/+4
| | | | llvm-svn: 146714
* Thumb2 ADR assembly parsing w/o the .w suffix.Jim Grosbach2011-12-151-0/+4
| | | | llvm-svn: 146710
* Make check a bit more strict so we don't call ARM_AM::getFP32Imm with a ↵Eli Friedman2011-12-151-1/+1
| | | | | | value that isn't a 32-bit value. (This is just to be safe; I don't think this actually causes any issues in practice.) llvm-svn: 146700
* ARM NEON VCLE is an alias for VCGE w/ the source operands reversed.Jim Grosbach2011-12-151-0/+32
| | | | llvm-svn: 146699
* ARM NEON VTBL/VTBX assembly parsing and encoding.Jim Grosbach2011-12-153-30/+23
| | | | llvm-svn: 146691
* Enable proper constant island alignment by default.Jakob Stoklund Olesen2011-12-151-1/+1
| | | | | | | The code size increase is tiny (< 0.05%) because so little code uses 16-byte constant pool entries. llvm-svn: 146690
* Silence warning.Jim Grosbach2011-12-151-1/+1
| | | | llvm-svn: 146686
* ARM NEON two-register double spaced register list parsing support.Jim Grosbach2011-12-151-14/+49
| | | | llvm-svn: 146685
* Consider CPE alignment in CreateNewWater().Jakob Stoklund Olesen2011-12-141-104/+117
| | | | | | | | | | | An aligned constant pool entry may require extra alignment padding where the new water is created. Take that into account when computing offset. Also consider the alignment of other constant pool entries when splitting a basic block. Alignment padding may make it necessary to move the split point higher. llvm-svn: 146609
* ARM NEON better assembly operand range checking for lane indices of VLD/VST.Jim Grosbach2011-12-142-33/+93
| | | | llvm-svn: 146608
* ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.Jim Grosbach2011-12-142-196/+420
| | | | llvm-svn: 146605
* ARM NEON fix alignment encoding for VST2 w/ writeback.Jim Grosbach2011-12-141-4/+4
| | | | | | Add tests for w/ writeback instruction parsing and encoding. llvm-svn: 146594
* Nuke old code. Missed in last commit.Jim Grosbach2011-12-141-14/+0
| | | | llvm-svn: 146590
* ARM NEON refactor VST2 w/ writeback instructions.Jim Grosbach2011-12-144-54/+130
| | | | | | | In addition to improving the representation, this adds support for assembly parsing of these instructions. llvm-svn: 146588
* ARM NEON improve factoring a bit. No functional change.Jim Grosbach2011-12-141-18/+12
| | | | llvm-svn: 146585
* Model ARM predicated write as read-mod-write. e.g.Evan Cheng2011-12-142-14/+45
| | | | | | | | | | | r0 = mov #0 r0 = moveq #1 Then the second instruction has an implicit data dependency on the first instruction. Sadly I have yet to come up with a small test case that demonstrate the post-ra scheduler taking advantage of this. llvm-svn: 146583
* ARM NEON VST2 assembly parsing and encoding.Jim Grosbach2011-12-145-76/+52
| | | | | | | | Work in progress. Parsing for non-writeback, single spaced register lists works now. The rest have the representations better factored, but still need more to be able to parse properly. llvm-svn: 146579
* Fix speling and 80-col.Jakob Stoklund Olesen2011-12-141-4/+3
| | | | llvm-svn: 146575
* Fix copy/pasto that skipped the 'modify' step.Jim Grosbach2011-12-141-4/+4
| | | | llvm-svn: 146571
* ARM/Thumb2 mov vs. mvn alias goes both ways.Jim Grosbach2011-12-142-0/+4
| | | | llvm-svn: 146570
* VFP2 is required for FP loads. Noticed by inspection.Chad Rosier2011-12-141-0/+2
| | | | llvm-svn: 146569
* Tidy up.Chad Rosier2011-12-141-1/+2
| | | | llvm-svn: 146568
* ARM/Thumb2 'cmp rn, #imm' alias to cmn.Jim Grosbach2011-12-142-1/+11
| | | | | | | | | | When 'cmp rn #imm' doesn't match due to the immediate not being representable, but 'cmn rn, #-imm' does match, use the latter in place of the former, as it's equivalent. rdar://10552389 llvm-svn: 146567
* Fix 80-column violation and extraneous brackets.Chad Rosier2011-12-141-8/+9
| | | | llvm-svn: 146566
* ARM assembler support for the target-specific .req directive.Jim Grosbach2011-12-141-1/+67
| | | | | | rdar://10549683 llvm-svn: 146543
* - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a functionEvan Cheng2011-12-149-56/+177
| | | | | | | | | | to finalize MI bundles (i.e. add BUNDLE instruction and computing register def and use lists of the BUNDLE instruction) and a pass to unpack bundles. - Teach more of MachineBasic and MachineInstr methods to be bundle aware. - Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to prevent IT blocks from being broken apart. llvm-svn: 146542
* Thumb2 assembler aliases for "mov(shifted register)"Jim Grosbach2011-12-132-1/+45
| | | | | | rdar://10549767 llvm-svn: 146520
* ARM LDM/STM system instruction variants.Jim Grosbach2011-12-132-11/+39
| | | | | | rdar://10550269 llvm-svn: 146519
* Thumb2 pre/post indexed stores can be from any non-PC GPR.Jim Grosbach2011-12-131-3/+3
| | | | | | rdar://10549786 llvm-svn: 146518
* Thumb2 tweak for ccout handling in RSB parsing.Jim Grosbach2011-12-131-1/+4
| | | | llvm-svn: 146516
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