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* Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. ↵Sylvestre Ledru2012-09-275-10/+10
| | | | | | See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767 llvm-svn: 164768
* Fix a typo 'iff' => 'if'Sylvestre Ledru2012-09-275-10/+10
| | | | llvm-svn: 164767
* [arm-fast-isel] Add support for ELF PIC.Jush Lu2012-09-275-2/+123
| | | | | | | This is a preliminary step towards ELF support; currently ARMFastISel hasn't been used for ELF object files yet. llvm-svn: 164759
* Remove the `hasFnAttr' method from Function.Bill Wendling2012-09-264-5/+5
| | | | | | | The hasFnAttr method has been replaced by querying the Attributes explicitly. No intended functionality change. llvm-svn: 164725
* Fix ordering of operands on lowering of atomicrmw min/max nodes on ARM.James Molloy2012-09-261-2/+2
| | | | llvm-svn: 164685
* ARM: Darwin BL/BLX relocations to out-of-range symbols.Jim Grosbach2012-09-251-1/+48
| | | | | | | | | | | When a BL/BLX references a symbol in the same translation unit that is out of range, use an external relocation. The linker will use this to generate a branch island rather than a direct reference, allowing the relocation to resolve correctly. rdar://12359919 llvm-svn: 164615
* ARM: 'add Rd, pc, #imm' is an alias for 'adr Rd, #imm'.Jim Grosbach2012-09-251-0/+14
| | | | | | rdar://9795790 llvm-svn: 164577
* Rather then have a wrapper function, have tblgen instantiate the implementation.Chad Rosier2012-09-241-6/+0
| | | | | | Also remove an unused argument. llvm-svn: 164567
* Rather then have a wrapper function, have tblgen instantiate the implementation.Chad Rosier2012-09-241-4/+0
| | | | llvm-svn: 164548
* ARMInstPrinter.cpp: Fix a warning in -Asserts. [-Wunused-variable]NAKAMURA Takumi2012-09-221-0/+2
| | | | llvm-svn: 164459
* Whitespace.NAKAMURA Takumi2012-09-221-2/+2
| | | | llvm-svn: 164458
* Fix edge cases of ARM shift operands in arith instructions.Tim Northover2012-09-221-38/+6
| | | | | | | | | As before with load instructions, oddities like "asr #32", "rrx" could be printed incorrectly. Patch by Chris Lidbury. llvm-svn: 164456
* Fix the handling of edge cases in ARM shifted operands.Tim Northover2012-09-224-8/+35
| | | | | | | | | This patch fixes load/store instructions to handle less common cases like "asr #32", "rrx" properly throughout the MC layer. Patch by Chris Lidbury. llvm-svn: 164455
* [ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser.Chad Rosier2012-09-211-0/+4
| | | | llvm-svn: 164420
* Add comment.Chad Rosier2012-09-211-1/+2
| | | | llvm-svn: 164414
* [fast-isel] Fallback to SelectionDAG isel if we require strict alignment forChad Rosier2012-09-211-0/+6
| | | | | | | non-aligned i32 loads/stores. rdar://12304911 llvm-svn: 164381
* Cortex-A9 latency fixes (w/ -schedmodel only).Andrew Trick2012-09-211-5/+5
| | | | | | Quick review against the manual revealed a few obvious mistakes. llvm-svn: 164361
* [fast-isel] Fallback to SelectionDAG isel if we require strict alignment forChad Rosier2012-09-211-0/+6
| | | | | | | non-halfword-aligned i16 loads/stores. rdar://12304911 llvm-svn: 164345
* Tidy up. Whitespace.Jim Grosbach2012-09-211-2/+2
| | | | llvm-svn: 164344
* Tidy up. Formatting.Jim Grosbach2012-09-211-1/+1
| | | | llvm-svn: 164343
* ARM: Use a dedicated intrinsic for vector bitwise select.Jim Grosbach2012-09-211-2/+29
| | | | | | | | | | | The expression based expansion too often results in IR level optimizations splitting the intermediate values into separate basic blocks, preventing the formation of the VBSL instruction as the code author intended. In particular, LICM would often hoist part of the computation out of a loop. rdar://11011471 llvm-svn: 164340
* Change enum type in a static table to uint8_t instead. Saves about 700 ↵Craig Topper2012-09-201-6/+6
| | | | | | hundred bytes of static data. Change unsigned char in same table to uint8_t for explicitness. llvm-svn: 164285
* MOVi16 (movw) is only legal on cpus with V6T2 support. rdar://12300648Evan Cheng2012-09-181-2/+4
| | | | llvm-svn: 164169
* When creating MCAsmBackend pass the CPU string as well. In X86AsmBackendRoman Divacky2012-09-182-2/+2
| | | | | | | | | store this and use it to not emit long nops when the CPU is geode which doesnt support them. Fixes PR11212. llvm-svn: 164132
* More domain conversion; convert VFP VMOVS to NEON instructions in more cases ↵James Molloy2012-09-181-13/+56
| | | | | | - when we may clobber the other S-lane by converting an S to a D instruction, make an effort to work out if the S lane is clobberable or not. llvm-svn: 164114
* TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵Andrew Trick2012-09-181-1/+2
| | | | | | model. llvm-svn: 164092
* Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byteEvan Cheng2012-09-182-5/+42
| | | | | | | | | aligned address. Based on patch by David Peixotto. Also use vld1.64 / vst1.64 with 128-bit alignment to take advantage of alignment hints. rdar://12090772, rdar://12238782 llvm-svn: 164089
* Revert r164061-r164067. Most of the new subtarget emitter.Andrew Trick2012-09-171-2/+1
| | | | | | | I have to work out the Target/CodeGen header dependencies before putting this back. llvm-svn: 164072
* TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵Andrew Trick2012-09-171-1/+2
| | | | | | model. llvm-svn: 164061
* Removed the VMLxForwarding feature for the Cortex-A15 target.Silviu Baranga2012-09-171-2/+1
| | | | llvm-svn: 164030
* Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments.Craig Topper2012-09-151-2/+2
| | | | llvm-svn: 163974
* Implement getNumLDMAddresses and expose through ARMBaseInstrInfo.Andrew Trick2012-09-142-0/+34
| | | | llvm-svn: 163922
* Cortex-A9 instruction-level scheduling machine model.Andrew Trick2012-09-141-3/+594
| | | | | | | | | | | | | | | | | | | | This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. llvm-svn: 163921
* Fix Doxygen issues:Dmitri Gribenko2012-09-141-1/+1
| | | | | | | | | | * wrap code blocks in \code ... \endcode; * refer to parameter names in paragraphs correctly (\arg is not what most people want -- it starts a new paragraph); * use \param instead of \arg to document parameters in order to be consistent with the rest of the codebase. llvm-svn: 163902
* This patch introduces A15 as a target in LLVM.Silviu Baranga2012-09-139-30/+41
| | | | llvm-svn: 163803
* Rename the isMemory() function to isMem(). No functional change intended.Chad Rosier2012-09-111-22/+22
| | | | llvm-svn: 163654
* Remove redundant semicolons which are null statements.Dmitri Gribenko2012-09-101-1/+1
| | | | llvm-svn: 163547
* Don't attempt to use flags from predicated instructions.Jakob Stoklund Olesen2012-09-101-2/+8
| | | | | | | | | | | | The ARM backend can eliminate cmp instructions by reusing flags from a nearby sub instruction with similar arguments. Don't do that if the sub is predicated - the flags are not written unconditionally. <rdar://problem/12263428> llvm-svn: 163535
* Set operation action for FFLOOR to Expand for all vector types for X86. Set ↵Craig Topper2012-09-081-0/+1
| | | | | | FFLOOR of v4f32 to Expand for ARM. v2f64 was already correct. llvm-svn: 163458
* Custom DAGCombine for and/or/xor are for all ARMs.Jakob Stoklund Olesen2012-09-071-6/+3
| | | | | | | The 'select' transformations apply to all ARM architectures and don't require hasV6T2Ops. llvm-svn: 163396
* MC: Overhaul handling of .lcommBenjamin Kramer2012-09-071-1/+0
| | | | | | | | | | | | | - Darwin lied about not supporting .lcomm and turned it into zerofill in the asm parser. Push the zerofill-conversion down into macho-specific code. - This makes the tri-state LCOMMType enum superfluous, there are no targets without .lcomm. - Do proper error reporting when trying to use .lcomm with alignment on a target that doesn't support it. - .comm and .lcomm alignment was parsed in bytes on COFF, should be power of 2. - Fixes PR13755 (.lcomm crashes on ELF). llvm-svn: 163395
* Diagnose invalid alignments on duplicating VLDn instructions.Tim Northover2012-09-061-0/+4
| | | | | | Patch by Chris Lidbury. llvm-svn: 163323
* Check for invalid alignment values when decoding VLDn/VSTn (single ln) ↵Tim Northover2012-09-061-8/+38
| | | | | | | | instructions. Patch by Chris Lidbury. llvm-svn: 163321
* Use correct part of complex operand to encode VST1 alignment.Tim Northover2012-09-061-2/+2
| | | | | | Patch by Chris Lidbury. llvm-svn: 163318
* Fix a few old-GCC warnings. No functional change.Nadav Rotem2012-09-061-1/+1
| | | | llvm-svn: 163309
* Fix self-host; ensure signedness is consistent.James Molloy2012-09-061-2/+2
| | | | llvm-svn: 163306
* Improve codegen for BUILD_VECTORs on ARM.James Molloy2012-09-061-10/+56
| | | | | | If we have a BUILD_VECTOR that is mostly a constant splat, it is often better to splat that constant then insertelement the non-constant lanes instead of insertelementing every lane from an undef base. llvm-svn: 163304
* Optimize codegen for VSETLNi{8,16,32} operating on Q registers. Degenerate ↵James Molloy2012-09-062-17/+66
| | | | | | to a VSETLN on D registers, instead of an (INSERT_SUBREG (VSETLN (EXTRACT_SUBREG ))) sequence to help the register coalescer. llvm-svn: 163298
* Remove predicated pseudo-instructions.Jakob Stoklund Olesen2012-09-052-100/+0
| | | | | | | These pseudos are no longer needed now that it is possible to represent predicated instructions in SSA form. llvm-svn: 163275
* Use predication instead of pseudo-opcodes when folding into MOVCC.Jakob Stoklund Olesen2012-09-051-56/+31
| | | | | | | | | | | | | | | | | | | | Now that it is possible to dynamically tie MachineInstr operands, predicated instructions are possible in SSA form: %vreg3<def> = SUBri %vreg1, -2147483647, pred:14, pred:%noreg, %opt:%noreg %vreg4<def,tied1> = MOVCCr %vreg3<tied0>, %vreg1, %pred:12, pred:%CPSR Becomes a predicated SUBri with a tied imp-use: SUBri %vreg1, -2147483647, pred:13, pred:%CPSR, opt:%noreg, %vreg1<imp-use,tied0> This means that any instruction that is safe to move can be folded into a MOVCC, and the *CC pseudo-instructions are no longer needed. The test case changes reflect that Thumb2SizeReduce recognizes the predicated instructions. It didn't understand the pseudos. llvm-svn: 163274
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