summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM
Commit message (Collapse)AuthorAgeFilesLines
* Tidy up. 80 column.Jim Grosbach2011-11-141-5/+8
| | | | llvm-svn: 144538
* Add support for ARM halfword load/stores and signed byte loads with negativeChad Rosier2011-11-141-8/+15
| | | | | | | offsets. rdar://10412592 llvm-svn: 144518
* The order in which the predicate is added differs between Thumb and ARM ↵Chad Rosier2011-11-131-10/+16
| | | | | | mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall. llvm-svn: 144494
* Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing ↵Chad Rosier2011-11-131-0/+1
| | | | | | failures. llvm-svn: 144492
* Fix comments.Chad Rosier2011-11-131-3/+3
| | | | llvm-svn: 144490
* Add support for emitting both signed- and zero-extend loads. Fix Chad Rosier2011-11-131-32/+91
| | | | | | | | | | | | | SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8 offsets (addressing mode 3). This enables a load followed by an integer extend to be folded into a single load. For example: ldrb r1, [r0] ldrb r1, [r0] uxtb r2, r1 => mov r3, r2 mov r3, r1 llvm-svn: 144488
* build: Attempt to rectify inconsistencies between CMake and LLVMBuild ↵Daniel Dunbar2011-11-123-3/+3
| | | | | | | | versions of explicit dependencies. - The hope is that we have a tool/test to verify these are accurate (and tight) soon. llvm-svn: 144444
* ARM refactor simple immediate asm operand render methods.Jim Grosbach2011-11-124-79/+22
| | | | | | | These immediate operands all use the same simple logic for rendering to MCInst, so have them share the method for doing so. llvm-svn: 144439
* Re-apply 144430, this time with the associated isel and disassmbler bits.Jim Grosbach2011-11-123-11/+6
| | | | | | Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.' llvm-svn: 144437
* Oops. Missed the isel half of this. revert while I sort that out.Jim Grosbach2011-11-111-3/+4
| | | | llvm-svn: 144431
* ARM assembly parsing for VST1 two-register encoding.Jim Grosbach2011-11-111-4/+3
| | | | llvm-svn: 144430
* ARM optional size suffix for VLDR/VSTR syntax.Jim Grosbach2011-11-111-0/+9
| | | | llvm-svn: 144427
* Add support in fast-isel for selecting memset/memcpy/memmove intrinsics.Chad Rosier2011-11-111-10/+60
| | | | llvm-svn: 144426
* ARM vldm and vstm VFP instructions can take a data type suffix.Jim Grosbach2011-11-111-0/+22
| | | | | | | | | | | | It's ignored by the assembler when present, but is legal syntax. Other instructions have something similar, but for some mnemonics it's only sometimes not significant, so this quick check in the parser will need refactored into something more robust soon-ish. This gets some basics working in the meantime. Partial for rdar://10435264 llvm-svn: 144422
* Nuke no longer accurate comment.Jim Grosbach2011-11-111-3/+0
| | | | llvm-svn: 144411
* Preserve MachineMemOperands in ARMLoadStoreOptimizer.Andrew Trick2011-11-111-0/+22
| | | | | | Fixes PR8113. llvm-svn: 144409
* ARM allow Q registers in vldm/vstm register lists.Jim Grosbach2011-11-111-27/+45
| | | | | | rdar://9672822 llvm-svn: 144407
* Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler.Benjamin Kramer2011-11-111-1/+1
| | | | llvm-svn: 144384
* Rename variables to avoid confusion. No functionallity change intended.Chad Rosier2011-11-111-18/+18
| | | | llvm-svn: 144377
* Add support for using immediates with select instructions.Chad Rosier2011-11-111-8/+40
| | | | | | rdar://10412592 llvm-svn: 144376
* Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3.Eli Friedman2011-11-111-0/+1
| | | | llvm-svn: 144361
* When loading a value, treat an i1 as an i8.Chad Rosier2011-11-111-0/+1
| | | | llvm-svn: 144356
* Add support for using MVN to materialize negative constants.Chad Rosier2011-11-111-3/+17
| | | | | | rdar://10412592 llvm-svn: 144348
* LLVMBuild: Add explicit information on whether targets define an assembly ↵Daniel Dunbar2011-11-111-0/+3
| | | | | | printer, assembly parser, or disassembler. llvm-svn: 144344
* Thumb2 ldm/stm updating w/ one register in the list are LDR/STR.Jim Grosbach2011-11-101-0/+32
| | | | | | rdar://10429490 llvm-svn: 144338
* ARM let processInstruction() tranforms chain.Jim Grosbach2011-11-101-15/+37
| | | | llvm-svn: 144337
* Thumb2 parsing for push/pop w/ hi registers in the reglist.Jim Grosbach2011-11-101-2/+32
| | | | | | rdar://10130228. llvm-svn: 144331
* Thumb1 diagnostics for reglist on PUSH/POP fix.Jim Grosbach2011-11-101-2/+2
| | | | | | Was not checking the first register in the register list. llvm-svn: 144329
* Thumb MUL assembly parsing for 3-operand form.Jim Grosbach2011-11-101-7/+9
| | | | | | | | | Get the source register that isn't tied to the destination register correct, even when the assembly source operand order is backwards. rdar://10428630 llvm-svn: 144322
* When in ARM mode, LDRH/STRH require special handling of negative offsets.Chad Rosier2011-11-101-1/+2
| | | | | | | For correctness, disable this for now. rdar://10418009 llvm-svn: 144316
* ARM .thumb_func directive for quoted symbol names.Jim Grosbach2011-11-101-3/+3
| | | | | | | | | Use the getIdentifier() method of the token, not getString(), otherwise we keep the quotes as part of the symbol name, which we don't want. rdar://10428015 llvm-svn: 144315
* ARM assembly parsing for LSR/LSL/ROR(immediate).Jim Grosbach2011-11-102-6/+50
| | | | | | More of rdar://9704684 llvm-svn: 144301
* ARM assembly parsing for ASR(immediate).Jim Grosbach2011-11-103-7/+37
| | | | | | Start of rdar://9704684 llvm-svn: 144293
* For immediate encodings of icmp, zero or sign extend first. ThenChad Rosier2011-11-101-5/+5
| | | | | | | determine if the value is negative and flip the sign accordingly. rdar://10422026 llvm-svn: 144258
* llvm-build: Add --native-target and --enable-targets options, and add logic toDaniel Dunbar2011-11-101-1/+0
| | | | | | | | | | handle defining the "magic" target related components (like native, nativecodegen, and engine). - We still require these components to be in the project (currently in lib/Target) so that we have a place to document them and hopefully make it more obvious that they are "magic". llvm-svn: 144253
* llvm-build: Add an explicit component type to represent targets.Daniel Dunbar2011-11-101-1/+2
| | | | | | - Gives us a place to hang target specific metadata (like whether the target has a JIT). llvm-svn: 144250
* Tidy up.Jim Grosbach2011-11-101-12/+0
| | | | llvm-svn: 144244
* Thumb2 assembly parsing STMDB w/ optional .w suffix.Jim Grosbach2011-11-091-0/+6
| | | | | | rdar://10422955 llvm-svn: 144242
* Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM.Eli Friedman2011-11-091-1/+25
| | | | llvm-svn: 144241
* The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12.Chad Rosier2011-11-091-5/+13
| | | | | | rdar://10418009 llvm-svn: 144213
* Add support for encoding immediates in icmp and fcmp. Hopefully, this willChad Rosier2011-11-091-12/+64
| | | | | | | remove a fair number of unnecessary materialized constants. rdar://10412592 llvm-svn: 144163
* Hide cpu name checking in ARMSubtarget.Evan Cheng2011-11-092-1/+2
| | | | llvm-svn: 144154
* Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ↵Evan Cheng2011-11-081-3/+9
| | | | | | ldm or ldr pairs. llvm-svn: 144123
* ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this.Chad Rosier2011-11-081-39/+39
| | | | | | No functional change intended. llvm-svn: 144122
* Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported.Lang Hames2011-11-081-0/+7
| | | | | | | | Add support for trimming constants to GetDemandedBits. This fixes some funky constant generation that occurs when stores are expanded for targets that don't support unaligned stores natively. llvm-svn: 144102
* Added invariant field to the DAG.getLoad method and changed all calls.Pete Cooper2011-11-082-33/+39
| | | | | | When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses llvm-svn: 144100
* Make sure to mark vector extload's as expand on ARM. Fixes PR11319.Eli Friedman2011-11-081-9/+11
| | | | llvm-svn: 144057
* Enable support for returning i1, i8, and i16. Nothing special todo as it's theChad Rosier2011-11-082-1/+9
| | | | | | | | callee's responsibility to sign or zero-extend the return value. The additional test case just checks to make sure the calls are selected (i.e., -fast-isel-abort doesn't assert). llvm-svn: 144047
* Allow i1 to be promoted to i32 for ARM AAPCS and AAPCS-VFP calling ↵Chad Rosier2011-11-071-1/+1
| | | | | | convention as well. llvm-svn: 144021
* Simplify some uses of utohexstr.Benjamin Kramer2011-11-071-2/+2
| | | | | | As a side effect hex is printed lowercase instead of uppercase now. llvm-svn: 144013
OpenPOWER on IntegriCloud