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* Revert r312724 ("[ARM] Remove redundant vcvt patterns.").Eli Friedman2017-09-251-0/+14
| | | | | | | | | | | | | | It leads to some improvements, but also a regression for the simple case, so it's not clearly a good idea. test/CodeGen/ARM/vcvt.ll now has test coverage to show the difference. Ultimately, the right solution is probably to custom-lower fp-to-int conversions, to something like ARMISD::VCVT_F32_S32 plus a bitcast. It's hard to do the right thing when the implicit bitcast isn't visible to DAG transforms. llvm-svn: 314169
* [SelectionDAG] Teach simplifyDemandedBits to handle shifts by constant splat ↵Craig Topper2017-09-251-0/+6
| | | | | | | | | | | | | | | | vectors This teach simplifyDemandedBits to handle constant splat vector shifts. This required changing some uses of getZExtValue to getLimitedValue since we can't rely on legalization using getShiftAmountTy for the shift amount. I believe there may have been a bug in the ((X << C1) >>u ShAmt) handling where we didn't check if the inner shift was too large. I've fixed that here. I had to add new patterns to ARM because the zext/sext the patterns were trying to look for got turned into an any_extend with this patch. Happy to split that out too, but not sure how to test without this change. Differential Revision: https://reviews.llvm.org/D37665 llvm-svn: 314139
* ARM: One more fix for swifterror CSR setArnold Schwaighofer2017-09-252-3/+11
| | | | | | | We use a differently ordered CSR set if the frame pointer is pushed. Add a matching ..._SwiftError version. llvm-svn: 314128
* [ARM] Fix -Wdangling-else warning.Benjamin Kramer2017-09-251-8/+4
| | | | | | A ternary is clearer here. No functionality change. llvm-svn: 314123
* ARM: Use the proper swifterror CSR list on platforms other than darwinArnold Schwaighofer2017-09-252-2/+11
| | | | | | Noticed by inspection llvm-svn: 314121
* [ARM] Fix assembly and disassembly for VMRS/VMSRAndre Vieira2017-09-223-35/+71
| | | | | | | Reviewed by: t.p.northover Differential Revision: https://reviews.llvm.org/D36306 llvm-svn: 313979
* [ARM] Add missing selection patterns for vnmlaSimon Pilgrim2017-09-221-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For the following function: double fn1(double d0, double d1, double d2) { double a = -d0 - d1 * d2; return a; } on ARM, LLVM generates code along the lines of vneg.f64 d0, d0 vmls.f64 d0, d1, d2 i.e., a negate and a multiply-subtract. The attached patch adds instruction selection patterns to allow it to generate the single instruction vnmla.f64 d0, d1, d2 (multiply-add with negation) instead, like GCC does. Committed on behalf of @gergo- (Gergö Barany) Differential Revision: https://reviews.llvm.org/D35911 llvm-svn: 313972
* [ARM] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-09-2017-233/+456
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 313823
* [ARM] Relax 'cpsie'/'cpsid' flag parsing.Jonathan Roelofs2017-09-191-1/+1
| | | | | | | | | | The ARM docs suggest in examples that the flags can have either case, and there are applications in the wild that (libopencm3, for example) that expect to be able to use the uppercase spelling. https://reviews.llvm.org/D37953 llvm-svn: 313680
* [ARM] Use ADDCARRY / SUBCARRYRoger Ferrer Ibanez2017-09-192-20/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is a preparatory step for D34515. This change: - makes nodes ISD::ADDCARRY and ISD::SUBCARRY legal for i32 - lowering is done by first converting the boolean value into the carry flag using (_, C) ← (ARMISD::ADDC R, -1) and converted back to an integer value using (R, _) ← (ARMISD::ADDE 0, 0, C). An ARMISD::ADDE between the two operations does the actual addition. - for subtraction, given that ISD::SUBCARRY second result is actually a borrow, we need to invert the value of the second operand and result before and after using ARMISD::SUBE. We need to invert the carry result of ARMISD::SUBE to preserve the semantics. - given that the generic combiner may lower ISD::ADDCARRY and ISD::SUBCARRYinto ISD::UADDO and ISD::USUBO we need to update their lowering as well otherwise i64 operations now would require branches. This implies updating the corresponding test for unsigned. - add new combiner to remove the redundant conversions from/to carry flags to/from boolean values (ARMISD::ADDC (ARMISD::ADDE 0, 0, C), -1) → C - fixes PR34045 - fixes PR34564 Differential Revision: https://reviews.llvm.org/D35192 llvm-svn: 313618
* [ARM] Implement isTruncateFreeSam Parker2017-09-182-1/+22
| | | | | | | | | | Implement the isTruncateFree hooks, lifted from AArch64, that are used by TargetTransformInfo. This allows simplifycfg to reduce the test case into a single basic block. Differential Revision: https://reviews.llvm.org/D37516 llvm-svn: 313533
* [ARM] Fix for indexed dot product instruction descriptionsSjoerd Meijer2017-09-181-1/+1
| | | | | | | | | | | The indexed dot product instructions only accept the lower 16 D-registers as the indexed register, but we were e.g. incorrectly accepting: vudot.u8 d16,d16,d18[0] Differential Revision: https://reviews.llvm.org/D37968 llvm-svn: 313531
* Revert r313009 "[ARM] Use ADDCARRY / SUBCARRY"Hans Wennborg2017-09-122-168/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was causing PR34045 to fire again. > This is a preparatory step for D34515 and also is being recommitted as its > first version caused PR34045. > > This change: > - makes nodes ISD::ADDCARRY and ISD::SUBCARRY legal for i32 > - lowering is done by first converting the boolean value into the carry flag > using (_, C) ← (ARMISD::ADDC R, -1) and converted back to an integer value > using (R, _) ← (ARMISD::ADDE 0, 0, C). An ARMISD::ADDE between the two > operations does the actual addition. > - for subtraction, given that ISD::SUBCARRY second result is actually a > borrow, we need to invert the value of the second operand and result before > and after using ARMISD::SUBE. We need to invert the carry result of > ARMISD::SUBE to preserve the semantics. > - given that the generic combiner may lower ISD::ADDCARRY and > ISD::SUBCARRYinto ISD::UADDO and ISD::USUBO we need to update their lowering > as well otherwise i64 operations now would require branches. This implies > updating the corresponding test for unsigned. > - add new combiner to remove the redundant conversions from/to carry flags > to/from boolean values (ARMISD::ADDC (ARMISD::ADDE 0, 0, C), -1) → C > - fixes PR34045 > > Differential Revision: https://reviews.llvm.org/D35192 Also revert follow-up r313010: > [ARM] Fix typo when creating ISD::SUB nodes > > In D35192, I accidentally introduced a typo when creating ISD::SUB nodes, > giving them two values instead of one. > > This fails when the merge_values combiner finds one of these nodes. > > This change fixes PR34564. > > Differential Revision: https://reviews.llvm.org/D37690 llvm-svn: 313044
* [ARM] Fix typo when creating ISD::SUB nodesRoger Ferrer Ibanez2017-09-121-5/+5
| | | | | | | | | | | | | In D35192, I accidentally introduced a typo when creating ISD::SUB nodes, giving them two values instead of one. This fails when the merge_values combiner finds one of these nodes. This change fixes PR34564. Differential Revision: https://reviews.llvm.org/D37690 llvm-svn: 313010
* [ARM] Use ADDCARRY / SUBCARRYRoger Ferrer Ibanez2017-09-122-20/+168
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is a preparatory step for D34515 and also is being recommitted as its first version caused PR34045. This change: - makes nodes ISD::ADDCARRY and ISD::SUBCARRY legal for i32 - lowering is done by first converting the boolean value into the carry flag using (_, C) ← (ARMISD::ADDC R, -1) and converted back to an integer value using (R, _) ← (ARMISD::ADDE 0, 0, C). An ARMISD::ADDE between the two operations does the actual addition. - for subtraction, given that ISD::SUBCARRY second result is actually a borrow, we need to invert the value of the second operand and result before and after using ARMISD::SUBE. We need to invert the carry result of ARMISD::SUBE to preserve the semantics. - given that the generic combiner may lower ISD::ADDCARRY and ISD::SUBCARRYinto ISD::UADDO and ISD::USUBO we need to update their lowering as well otherwise i64 operations now would require branches. This implies updating the corresponding test for unsigned. - add new combiner to remove the redundant conversions from/to carry flags to/from boolean values (ARMISD::ADDC (ARMISD::ADDE 0, 0, C), -1) → C - fixes PR34045 Differential Revision: https://reviews.llvm.org/D35192 llvm-svn: 313009
* Revert r312898 "[ARM] Use ADDCARRY / SUBCARRY"Hans Wennborg2017-09-112-168/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | It caused PR34564. > This is a preparatory step for D34515 and also is being recommitted as its > first version caused PR34045. > > This change: > - makes nodes ISD::ADDCARRY and ISD::SUBCARRY legal for i32 > - lowering is done by first converting the boolean value into the carry flag > using (_, C) ← (ARMISD::ADDC R, -1) and converted back to an integer value > using (R, _) ← (ARMISD::ADDE 0, 0, C). An ARMISD::ADDE between the two > operations does the actual addition. > - for subtraction, given that ISD::SUBCARRY second result is actually a > borrow, we need to invert the value of the second operand and result before > and after using ARMISD::SUBE. We need to invert the carry result of > ARMISD::SUBE to preserve the semantics. > - given that the generic combiner may lower ISD::ADDCARRY and > ISD::SUBCARRYinto ISD::UADDO and ISD::USUBO we need to update their lowering > as well otherwise i64 operations now would require branches. This implies > updating the corresponding test for unsigned. > - add new combiner to remove the redundant conversions from/to carry flags > to/from boolean values (ARMISD::ADDC (ARMISD::ADDE 0, 0, C), -1) → C > - fixes PR34045 > > Differential Revision: https://reviews.llvm.org/D35192 llvm-svn: 312980
* [ARM] Enable the use of SVC anywhere in an IT blockAndre Vieira2017-09-111-3/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D37374 llvm-svn: 312908
* [ARM] Use ADDCARRY / SUBCARRYRoger Ferrer Ibanez2017-09-112-20/+168
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is a preparatory step for D34515 and also is being recommitted as its first version caused PR34045. This change: - makes nodes ISD::ADDCARRY and ISD::SUBCARRY legal for i32 - lowering is done by first converting the boolean value into the carry flag using (_, C) ← (ARMISD::ADDC R, -1) and converted back to an integer value using (R, _) ← (ARMISD::ADDE 0, 0, C). An ARMISD::ADDE between the two operations does the actual addition. - for subtraction, given that ISD::SUBCARRY second result is actually a borrow, we need to invert the value of the second operand and result before and after using ARMISD::SUBE. We need to invert the carry result of ARMISD::SUBE to preserve the semantics. - given that the generic combiner may lower ISD::ADDCARRY and ISD::SUBCARRYinto ISD::UADDO and ISD::USUBO we need to update their lowering as well otherwise i64 operations now would require branches. This implies updating the corresponding test for unsigned. - add new combiner to remove the redundant conversions from/to carry flags to/from boolean values (ARMISD::ADDC (ARMISD::ADDE 0, 0, C), -1) → C - fixes PR34045 Differential Revision: https://reviews.llvm.org/D35192 llvm-svn: 312898
* [ARM] Remove redundant vcvt patterns.Benjamin Kramer2017-09-071-14/+0
| | | | | | | | These don't add any value as they're just compositions of existing patterns. However, they can confuse the cost logic in ISel, leading to duplicated vcvt instructions like in PR33199. llvm-svn: 312724
* ARM: track globals promoted to coalesced const pool entriesSaleem Abdulrasool2017-09-073-13/+27
| | | | | | | | | | | | | Globals that are promoted to an ARM constant pool may alias with another existing constant pool entry. We need to keep a reference to all globals that were promoted to each constant pool value so that we can emit a distinct label for each promoted global. These labels are necessary so that debug info can refer to the promoted global without an undefined reference during linking. Patch by Stephen Crane! llvm-svn: 312692
* Insert IMPLICIT_DEFS for undef uses in tail mergingMatthias Braun2017-09-061-12/+10
| | | | | | | | | | | | | | | | | | | | | Tail merging can convert an undef use into a normal one when creating a common tail. Doing so can make the register live out from a block which previously contained the undef use. To keep the liveness up-to-date, insert IMPLICIT_DEFs in such blocks when necessary. To enable this patch the computeLiveIns() function which used to compute live-ins for a block and set them immediately is split into new functions: - computeLiveIns() just computes the live-ins in a LivePhysRegs set. - addLiveIns() applies the live-ins to a block live-in list. - computeAndAddLiveIns() is a convenience function combining the other two functions and behaving like computeLiveIns() before this patch. Based on a patch by Krzysztof Parzyszek <kparzysz@codeaurora.org> Differential Revision: https://reviews.llvm.org/D37034 llvm-svn: 312668
* [ARM] Make ARMExpandPseudo add implicit uses for predicated instructionsEli Friedman2017-09-051-8/+26
| | | | | | | | | | | Missing these could potentially screw up post-ra scheduling. Issue found by inspection, so I don't have a real testcase. Included test just verifies the expected operands after expansion. Differential Revision: https://reviews.llvm.org/D35156 llvm-svn: 312589
* [ARM] Register ARMExpandPseudo pass.Eli Friedman2017-09-053-1/+8
| | | | | | | | This allows -run-pass etc. to refer to it. (Split off from D35156.) llvm-svn: 312587
* [ARM] GlobalISel: Minor cleanups in inst selectorDiana Picus2017-09-051-11/+10
| | | | | | | | Use the STI member of ARMInstructionSelector instead of TII.getSubtarget() and also make use of STI's methods instead of checking the object format manually. llvm-svn: 312522
* [ARM] GlobalISel: Support global variables for RWPIDiana Picus2017-09-051-15/+51
| | | | | | | | | In RWPI code, globals that are not read-only are accessed relative to the SB register (R9). This is achieved by explicitly generating an ADD instruction between SB and an offset that we either load from a constant pool or movw + movt into a register. llvm-svn: 312521
* [ARM] GlobalISel: Support ROPI global variablesDiana Picus2017-09-011-2/+14
| | | | | | | In the ROPI relocation model, read-only variables are accessed relative to the PC. We use the (MOV|LDRLIT)_ga_pcrel pseudoinstructions for this. llvm-svn: 312323
* [ARM] Add 2-operand assembly aliases for Thumb1 ADD/SUBOliver Stannard2017-09-011-0/+6
| | | | | | | | | | | | | | | | This adds 2-operand assembly aliases for these instructions: add r0, r1 => add r0, r0, r1 sub r0, r1 => sub r0, r0, r1 Previously this syntax was only accepted for Thumb2 targets, where the wide versions of the instructions were used. This patch allows the 2-operand syntax to be used for Thumb1 targets, and selects the narrow encoding when it is used for Thumb2 targets. Differential revision: https://reviews.llvm.org/D37377 llvm-svn: 312321
* Move static helper into ARMTargetLowering. NFCDiana Picus2017-09-012-1/+3
| | | | | | | This exposes the isReadOnly(GlobalValue *) in the ARMTargetLowering so we can make use of it in GlobalISel as well. llvm-svn: 312320
* [ARM] Reverse PostRASched subtarget feature logicSam Parker2017-08-314-24/+17
| | | | | | | | | | | | Replace the UsePostRAScheduler SubtargetFeature with DisablePostRAScheduler, which is then used by Swift and Cyclone. This patch maintains enabling PostRA scheduling for other Thumb2 capable cores and/or for functions which are being compiled in Arm mode. Differential Revision: https://reviews.llvm.org/D37055 llvm-svn: 312226
* [ARM] Replace fixed-size SmallSet with a bitset.Benjamin Kramer2017-08-301-30/+30
| | | | | | It's smaller. No functionality change. llvm-svn: 312180
* [ARM] Use Swift error registers on non-Darwin targetsBrian Gesiak2017-08-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Remove a check for `ARMSubtarget::isTargetDarwin` when determining whether to use Swift error registers, so that Swift errors work properly on non-Darwin ARM32 targets (specifically Android). Before this patch, generated code would save and restores ARM register r8 at the entry and returns of a function that throws. As r8 is used as a virtual return value for the object being thrown, this gets overwritten by the restore, and calling code is unable to catch the error. In turn this caused Swift code that used `do`/`try`/`catch` to work improperly on Android ARM32 targets. Addresses Swift bug report https://bugs.swift.org/browse/SR-5438. Patch by John Holdsworth. Reviewers: manmanren, rjmccall, aschwaighofer Reviewed By: aschwaighofer Subscribers: srhines, aschwaighofer, aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D35835 llvm-svn: 312164
* [ARM] - Tidy-up ARMAsmPrinter.cppJaved Absar2017-08-291-10/+8
| | | | | | | | | Change to range-loop where missing. Reviwewed by: @fhahn, @asb Differential Revision: https://reviews.llvm.org/D37199 llvm-svn: 311993
* [ARM] GlobalISel: Select globals in PIC modeDiana Picus2017-08-294-7/+37
| | | | | | | | | | | | | | Support the selection of G_GLOBAL_VALUE in the PIC relocation model. For simplicity we use the same pseudoinstructions for both Darwin and ELF: (MOV|LDRLIT)_ga_pcrel(_ldr). This is new for ELF, so it requires a small update to the ARM pseudo expansion pass to make sure it adds the correct constant pool modifier and add-current-address in the case of ELF. Differential Revision: https://reviews.llvm.org/D36507 llvm-svn: 311992
* Fix ARMv4 supportJoerg Sonnenberger2017-08-289-10/+35
| | | | | | | | | | | | | | | | | | ARMv4 doesn't support the "BX" instruction, which has been introduced with ARMv4t. Adjust the call lowering and tail call implementation accordingly. Further changes are necessary to ensure that presence of the v4t feature is correctly set. Most importantly, the "generic" CPU for thumb-* triples should include ARMv4t, since thumb mode without thumb support would naturally be pointless. Add a couple of asserts to ensure thumb instructions are not emitted without CPU support. Differential Revision: https://reviews.llvm.org/D37030 llvm-svn: 311921
* [ARM] Fix bug in ARMLoadStoreOptimizer when kill flags are missing.Geoff Berry2017-08-281-30/+19
| | | | | | | | | | | | | | | | | | | | | | Summary: ARMLoadStoreOpt::FixInvalidRegPairOp() was only checking if one of the load destination registers to be split overlapped with the base register if the base register was marked as killed. Since kill flags may not always be present, this can lead to incorrect code. This bug was exposed by my MachineCopyPropagation change D30751 breaking the sanitizer-x86_64-linux-android buildbot. Also clean up some dead code and add an assert that a register offset is never encountered by this code, since it does not handle them correctly. Reviewers: MatzeB, qcolombet, t.p.northover Subscribers: aemerson, javed.absar, kristof.beyls, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D37164 llvm-svn: 311907
* Untabify.NAKAMURA Takumi2017-08-281-4/+4
| | | | llvm-svn: 311875
* [ARM] Tidy-up condition-code support functionsJaved Absar2017-08-273-102/+89
| | | | | | | | | Move condition code support functions to Utils and remove code duplication. Reviewed by: @fhahn, @asb Differential Revision: https://reviews.llvm.org/D37179 llvm-svn: 311860
* [ARM] Tidy-up ARMAsmParser. NFC.Javed Absar2017-08-271-23/+5
| | | | | | | | | Simplify getDRegFromQReg function Reviewed by: @fhahn, @asb Differential Revision: https://reviews.llvm.org/D37118 llvm-svn: 311850
* [ARM, Thumb1] Prevent ARMTargetLowering::isLegalAddressingMode from ↵Evgeny Astigeevich2017-08-242-4/+22
| | | | | | | | | | | | | | accepting illegal modes ARMTargetLowering::isLegalAddressingMode can accept illegal addressing modes for the Thumb1 target. This causes generation of redundant code and affects performance. This fixes PR34106: https://bugs.llvm.org/show_bug.cgi?id=34106 Differential Revision: https://reviews.llvm.org/D36467 llvm-svn: 311649
* ARM: use internal relocations for local symbols after all.Tim Northover2017-08-231-2/+11
| | | | | | | | | | | Switching to external relocations for ARM-mode branches (to allow Thumb interworking when the offset is unencodable) causes calls to temporary symbols to be miscompiled and instead go to the parent externally visible symbol. Calling a temporary never happens in compiled code, but can occasionally in hand-written assembly. llvm-svn: 311611
* [GISEl]: Translate phi into G_PHIAditya Nandakumar2017-08-231-1/+1
| | | | | | | | | | G_PHI has the same semantics as PHI but also has types. This lets us verify that the types in the G_PHI are consistent. This also allows specifying legalization actions for G_PHIs. https://reviews.llvm.org/D36990 llvm-svn: 311596
* [ARM] Add missing patterns for insert_subvector.Florian Hahn2017-08-231-0/+16
| | | | | | | | | | | | | | Summary: In some cases, shufflevector instruction can be transformed involving insert_subvector instructions. The ARM backend was missing some insert_subvector patterns, causing a failure during instruction selection. AArch64 has similar patterns. Reviewers: t.p.northover, olista01, javed.absar, rengolin Reviewed By: javed.absar Subscribers: aemerson, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D36796 llvm-svn: 311543
* TargetInstrInfo: Change duplicate() to work on bundles.Matthias Braun2017-08-222-15/+25
| | | | | | | | | | | | | | Adds infrastructure to clone whole instruction bundles rather than just single instructions. This fixes a bug where tail duplication would unbundle instructions while cloning. This should unbreak the "Clang Stage 1: cmake, RA, with expensive checks enabled" build on greendragon. The bot broke with r311139 hitting this pre-existing bug. A proper testcase will come next. llvm-svn: 311511
* [ARM][AArch64] v8.3-A Javascript ConversionSam Parker2017-08-221-0/+9
| | | | | | | | | | Armv8.3-A adds instructions that convert a double-precision floating point number to a signed 32-bit integer with round towards zero, designed for improving Javascript performance. Differential Revision: https://reviews.llvm.org/D36785 llvm-svn: 311448
* [ARM] Call setBooleanContents(ZeroOrOneBooleanContent)Renato Golin2017-08-221-0/+1
| | | | | | | | | | | The ARM backend should call setBooleanContents so that it can use known bits to make some optimizations. Review: D35821 Patch by Joel Galenson <jgalenson@google.com> llvm-svn: 311446
* Fix a typo in r311435.Chandler Carruth2017-08-221-1/+1
| | | | llvm-svn: 311437
* Use report_fatal_error for unsupported calling conventionsAlex Bradbury2017-08-222-4/+4
| | | | | | | | | | | The calling convention can be specified by the user in IR. Failing to support a particular calling convention isn't a programming error, and so relying on llvm_unreachable to catch and report an unsupported calling convention is not appropriate. Differential Revision: https://reviews.llvm.org/D36830 llvm-svn: 311435
* [ARM][AArch64] Cortex-A75 and Cortex-A55 supportSam Parker2017-08-213-0/+18
| | | | | | | | | | | | | | | | | | This patch introduces support for Cortex-A75 and Cortex-A55, Arm's latest big.LITTLE A-class cores. They implement the ARMv8.2-A architecture, including the cryptography and RAS extensions, plus the optional dot product extension. They also implement the RCpc AArch64 extension from ARMv8.3-A. Cortex-A75: https://developer.arm.com/products/processors/cortex-a/cortex-a75 Cortex-A55: https://developer.arm.com/products/processors/cortex-a/cortex-a55 Differential Revision: https://reviews.llvm.org/D36667 llvm-svn: 311316
* [ARM] Factorize the calculation of WhichResult in isV*Mask. NFC.Martin Storsjo2017-08-191-24/+13
| | | | | | Differential Revision: https://reviews.llvm.org/D36930 llvm-svn: 311260
* [ARM] Check the right order for halves of VZIP/VUZP if both parts are usedMartin Storsjo2017-08-191-4/+16
| | | | | | | | | | | | This is the exact same fix as in SVN r247254. In that commit, the fix was applied only for isVTRNMask and isVTRN_v_undef_Mask, but the same issue is present for VZIP/VUZP as well. This fixes PR33921. Differential Revision: https://reviews.llvm.org/D36899 llvm-svn: 311258
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