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* [ARM] Honor -mfloat-abi for libcall calling conventionEli Friedman2017-10-261-9/+1
| | | | | | | | | | | | | | | As far as I can tell, this matches gcc: -mfloat-abi determines the calling convention for all functions except those explicitly defined as soft-float in the ARM RTABI. This change only affects cases where the user specifies -mfloat-abi to override the default calling convention derived from the target triple. Fixes https://bugs.llvm.org//show_bug.cgi?id=34530. Differential Revision: https://reviews.llvm.org/D38299 llvm-svn: 316708
* Clear LastMappingSymbols and LastEMS(Info) when resetting the ↵Yichao Yu2017-10-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | ARM(AArch64)ELFStreamer Summary: This causes a segfault on ARM when (I think) the pass manager is used multiple times. Reset set the (last) current section to NULL without saving the corresponding LastEMSInfo back into the map. The next use of the streamer then save the LastEMSInfo for the NULL section leaving the LastEMSInfo mapping for the last current section (the one that was there before the reset) NULL which cause the LastEMSInfo to be set to NULL when the section is being used again. The reuse of the section (pointer) might mean that the map was holding dangling pointers previously which is why I went for clearing the map and resetting the info, making it as similar to the state right after the constructor run as possible. The AArch64 one doesn't have segfault (since LastEMS isn't a pointer) but it seems to have the same issue. The segfault is likely caused by https://reviews.llvm.org/D30724 which turns LastEMSInfo into a pointer. As mentioned above, it seems that the actual issue was older though. No test is included since the test is believed to be too complicated for such an obvious fix and not worth doing. Reviewers: llvm-commits, shankare, t.p.northover, peter.smith, rengolin Reviewed By: rengolin Subscribers: mgorny, aemerson, rengolin, javed.absar, kristof.beyls Differential Revision: https://reviews.llvm.org/D38588 llvm-svn: 316679
* [AsmParser][TableGen] Add VariantID argument to the generated mnemonic spell ↵Craig Topper2017-10-261-1/+2
| | | | | | | | check function so it can use the correct table based on variant. I'm considering implementing the mnemonic spell checker for x86, and that would require the separate intel and att variants. llvm-svn: 316641
* [AsmParser][TableGen] Make the generated mnemonic spell checker function a ↵Craig Topper2017-10-261-1/+2
| | | | | | | | file local static function. Also only emit in targets that specificially request it. This is required so we don't get an unused static function error. llvm-svn: 316640
* [ARM GlobalISel] Fix call opcodesDiana Picus2017-10-251-4/+11
| | | | | | | | We were generating BLX for all the calls, which was incorrect in most cases. Update ARMCallLowering to generate BL for direct calls, and BLX, BX_CALL or BMOVPCRX_CALL for indirect calls. llvm-svn: 316570
* [ARM] OrCombineToBFI functionSam Parker2017-10-251-92/+109
| | | | | | | | Extract the functionality to combine OR to BFI into its own function. Differential Revision: https://reviews.llvm.org/D39001 llvm-svn: 316563
* [ARM] Swap cmp operands for automatic shiftsSam Parker2017-10-251-0/+6
| | | | | | | | | | Swap the compare operands if the lhs is a shift and the rhs isn't, as in arm and T2 the shift can be performed by the compare for its second operand. Differential Revision: https://reviews.llvm.org/D39004 llvm-svn: 316562
* ARMAddressingModes.h: Don't mark header functions as file localDavid Blaikie2017-10-241-86/+63
| | | | llvm-svn: 316517
* [ARM] Error for invalid shift in memory operandOliver Stannard2017-10-241-1/+1
| | | | | | | | | | Report a diagnostic when we fail to parse a shift in a memory operand because the shift type is not an identifier. Without this, we were silently ignoring the whole instruction. Differential revision: https://reviews.llvm.org/D39237 llvm-svn: 316441
* [ARM] Replace development diagnostics with normal DEBUG macroOliver Stannard2017-10-241-14/+9
| | | | | | | | | | * Remove the -arm-asm-parser-dev-diags option. * Use normal DEBUG(dbgs()) printing for the extra development information about missing diagnostics. Differential Revision: https://reviews.llvm.org/D39194 llvm-svn: 316423
* [ARM] tSETEND needs IsThumbOliver Stannard2017-10-241-1/+1
| | | | | | | | | | This is the Thumb encoding, so the Requires list must include IsThumb. No test because we happen to select the ARM one first, but that's just luck. Differential Revision: https://reviews.llvm.org/D39190 llvm-svn: 316421
* [ARM] Remove tCPS alias which just crashedOliver Stannard2017-10-241-7/+0
| | | | | | | | | | | | This alias caused a crash when trying to print the "cps #0" instruction in a diagnostic for thumbv6 (which doesn't have that instruction). The comment was incorrect, this instruction is UNPREDICTABLE if no flag bits are set, so I don't think it's worth keeping. Differential Revision: https://reviews.llvm.org/D39191 llvm-svn: 316420
* [ARM] Allow unrolling of multi-block loops.Sam Parker2017-10-231-16/+35
| | | | | | | | | | | Before, loop unrolling was only enabled for loops with a single block. This restriction has been removed and replaced by: - allow a maximum of two exiting blocks, - a four basic block limit for cores with a branch predictor. Differential Revision: https://reviews.llvm.org/D38952 llvm-svn: 316313
* [ARM] Dynamic stack alignment for 16-bit ThumbMomchil Velikov2017-10-223-16/+38
| | | | | | | | | | | This patch implements dynamic stack (re-)alignment for 16-bit Thumb. When targeting processors, which support only the 16-bit Thumb instruction set the compiler ignores the alignment attributes of automatic variables and may silently generate incorrect code. Differential revision: https://reviews.llvm.org/D38143 llvm-svn: 316289
* [ARM] Use post-RA MI scheduler when +use-misched is setEugene Leviant2017-10-201-1/+8
| | | | | | Differential revision: https://reviews.llvm.org/D39100 llvm-svn: 316214
* [ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM modeAndre Vieira2017-10-181-2/+8
| | | | | | Differential Revision: https://reviews.llvm.org/D38347 llvm-svn: 316085
* Untabify.NAKAMURA Takumi2017-10-181-1/+1
| | | | llvm-svn: 316079
* Reverting r315590; it did not include changes for llvm-tblgen, which is ↵Aaron Ballman2017-10-152-2/+2
| | | | | | | | causing link errors for several people. Error LNK2019 unresolved external symbol "public: void __cdecl `anonymous namespace'::MatchableInfo::dump(void)const " (?dump@MatchableInfo@?A0xf4f1c304@@QEBAXXZ) referenced in function "public: void __cdecl `anonymous namespace'::AsmMatcherEmitter::run(class llvm::raw_ostream &)" (?run@AsmMatcherEmitter@?A0xf4f1c304@@QEAAXAEAVraw_ostream@llvm@@@Z) llvm-tblgen D:\llvm\2017\utils\TableGen\AsmMatcherEmitter.obj 1 llvm-svn: 315854
* Revert "TargetMachine: Merge TargetMachine and LLVMTargetMachine"Matthias Braun2017-10-122-4/+4
| | | | | | | | | | Reverting to investigate layering effects of MCJIT not linking libCodeGen but using TargetMachine::getNameWithPrefix() breaking the lldb bots. This reverts commit r315633. llvm-svn: 315637
* TargetMachine: Merge TargetMachine and LLVMTargetMachineMatthias Braun2017-10-122-4/+4
| | | | | | | | | | | | | | | Merge LLVMTargetMachine into TargetMachine. - There is no in-tree target anymore that just implements TargetMachine but not LLVMTargetMachine. - It should still be possible to stub out all the various functions in case a target does not want to use lib/CodeGen - This simplifies the code and avoids methods ending up in the wrong interface. Differential Revision: https://reviews.llvm.org/D38489 llvm-svn: 315633
* [dump] Remove NDEBUG from test to enable dump methods [NFC]Don Hinton2017-10-122-2/+2
| | | | | | | | | | | | | | | Summary: Add LLVM_FORCE_ENABLE_DUMP cmake option, and use it along with LLVM_ENABLE_ASSERTIONS to set LLVM_ENABLE_DUMP. Remove NDEBUG and only use LLVM_ENABLE_DUMP to enable dump methods. Move definition of LLVM_ENABLE_DUMP from config.h to llvm-config.h so it'll be picked up by public headers. Differential Revision: https://reviews.llvm.org/D38406 llvm-svn: 315590
* [MC] Have MCObjectStreamer take its MCAsmBackend argument via unique_ptr.Lang Hames2017-10-114-24/+29
| | | | | | | | MCObjectStreamer owns its MCCodeEmitter -- this fixes the types to reflect that, and allows us to remove the last instance of MCObjectStreamer's weird "holding ownership via someone else's reference" trick. llvm-svn: 315531
* [Asm] Add debug tracing in table-generated assembly matcherOliver Stannard2017-10-111-2/+1
| | | | | | | | | | | | | This adds debug tracing to the table-generated assembly instruction matcher, enabled by the -debug-only=asm-matcher option. The changes in the target AsmParsers are to add an MCInstrInfo reference under a consistent name, so that we can use it from table-generated code. This was already being used this way for targets that use deprecation warnings, but 5 targets did not have it, and Hexagon had it under a different name to the other backends. llvm-svn: 315445
* [MC] Have MCObjectStreamer take its MCAsmBackend argument via unique_ptr.Lang Hames2017-10-114-27/+38
| | | | | | | | MCObjectStreamer owns its MCAsmBackend -- this fixes the types to reflect that, and allows us to remove another instance of MCObjectStreamer's weird "holding ownership via someone else's reference" trick. llvm-svn: 315410
* [MC] Add another missing <memory> include left out of r315327.Lang Hames2017-10-101-0/+1
| | | | llvm-svn: 315332
* [MC] Thread unique_ptr<MCObjectWriter> through the create.*ObjectWriterLang Hames2017-10-107-18/+25
| | | | | | | | | | functions. This makes the ownership of the resulting MCObjectWriter clear, and allows us to remove one instance of MCObjectStreamer's bizarre "holding ownership via someone else's reference" trick. llvm-svn: 315327
* [ARM, Asm] Harden GNU LDRD/STRD aliases against invalid inputsOliver Stannard2017-10-101-19/+49
| | | | | | | | | | | | | | | | | | | Previously, the code that implemented the GNU assembler aliases for the LDRD and STRD instructions (where the second register is omitted) assumed that the input was a valid instruction. This caused assertion failures for every example in ldrd-strd-gnu-bad-inst.s. This improves this code so that it bails out if the instruction is not in the expected format, the check bails out, and the asm parser is run on the unmodified instruction. It also relaxes the alias on thumb targets, so that unaligned pairs of registers can be used. The restriction that Rt must be even-numbered only applies to the ARM versions of these instructions. Differential revision: https://reviews.llvm.org/D36732 llvm-svn: 315305
* [ARM, Asm] Add diagnostics for floating-point register operandsOliver Stannard2017-10-102-5/+22
| | | | | | | | | | | | | | | This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
* [ARM, Asm] Add diagnostics for general-purpose register operandsOliver Stannard2017-10-102-5/+34
| | | | | | | | | | | | | | | This adds diagnostic strings for the ARM general-purpose register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, rGPR, requires C++ code to select the correct error message, as that class contains different registers in pre-v8 and v8 targets. The rest can all have their diagnostic strings stored in the tablegen description of them. Differential revision: https://reviews.llvm.org/D36692 llvm-svn: 315303
* [MC] Plumb unique_ptr<MCWinCOFFObjectTargetWriter> throughLang Hames2017-10-101-2/+2
| | | | | | | | | | | createWinCOFFObjectWriter to WinCOFFObjectWriter's constructor. Fixes the same ownership issue for COFF that r315245 did for MachO: WinCOFFObjectWriter takes ownership of its MCWinCOFFObjectTargetWriter, so we want to pass this through to the constructor via a unique_ptr, rather than a raw ptr. llvm-svn: 315257
* [MC] Plumb unique_ptr<MCELFObjectTargetWriter> through createELFObjectWriter toLang Hames2017-10-091-2/+2
| | | | | | | | | | ELFObjectWriter's constructor. Fixes the same ownership issue for ELF that r315245 did for MachO: ELFObjectWriter takes ownership of its MCELFObjectTargetWriter, so we want to pass this through to the constructor via a unique_ptr, rather than a raw ptr. llvm-svn: 315254
* [MC] Plumb unique_ptr<MCMachObjectTargetWriter> through createMachObjectWriterLang Hames2017-10-091-4/+3
| | | | | | | | | | | to MCObjectWriter's constructor. MCObjectWriter takes ownership of its MCMachObjectTargetWriter argument -- this patch plumbs that ownership relationship through the constructor (which previously took raw MCMachObjectTargetWriter*) and the createMachObjectWriter function. llvm-svn: 315245
* [GISel]: Fix generation of illegal COPYs during CallLoweringAditya Nandakumar2017-10-091-5/+18
| | | | | | | | | | | We end up creating COPY's that are either truncating/extending and this should be illegal. https://reviews.llvm.org/D37640 Patch for X86 and ARM by igorb, rovka llvm-svn: 315240
* [ARM] GlobalISel: Select shiftsDiana Picus2017-10-061-0/+16
| | | | | | | | | Unfortunately TableGen doesn't handle this yet: Unable to deduce gMIR opcode to handle Src (which is a leaf). Just add some temporary hand-written code to generate the proper MOVsr. llvm-svn: 315071
* [ARM] GlobalISel: Map shift operands to GPRsDiana Picus2017-10-061-0/+3
| | | | llvm-svn: 315067
* [ARM] GlobalISel: Mark shifts as legal for s32Diana Picus2017-10-061-0/+3
| | | | | | | The new legalize combiner introduces shifts all over the place, so we should support them sooner rather than later. llvm-svn: 315064
* [ARM] Add diag string for movw/movt immediates in assemblyOliver Stannard2017-10-041-0/+1
| | | | | | | | | This adds diagnostics for invalid immediate operands to the MOVW and MOVT instructions (ARM and Thumb). Differential revision: https://reviews.llvm.org/D31879 llvm-svn: 314888
* [ARM, Asm] Change grammar of immediate operand diagnosticsOliver Stannard2017-10-041-3/+3
| | | | | | | | | | | | | | | | | Currently, our diagnostics for assembly operands are not consistent. Some start with (for example) "immediate operand must be ...", and some with "operand must be an immediate ...". I think the latter form is preferable for a few reasons: * It's unambiguous that it is referring to the expected type of operand, not the type the user provided. For example, the user could provide an register operand, and get a message taking about an operand is if it is already an immediate, just not in the accepted range. * It allows us to have a consistent style once we add diagnostics for operands that could take two forms, for example a label or pc-relative memory operand. Differential revision: https://reviews.llvm.org/D36689 llvm-svn: 314887
* [ARM] Use table-gen'd assembly operand diags in ARM asm parserOliver Stannard2017-10-033-95/+22
| | | | | | | | | | | | This switches the ARM AsmParser to use assembly operand diagnostics from tablegen, rather than a switch statement on the ARMMatchResultTy. It moves the existing diagnostic strings to tablegen, but adds no new ones, so this is NFC except for one diagnostic string that had an off-by-1 error in the hand-written switch statement. Differential revision: https://reviews.llvm.org/D31607 llvm-svn: 314804
* [ARM, Asm] Use correct source location for register tokensOliver Stannard2017-10-031-3/+3
| | | | | | | | | | | | tryParseRegister advances the lexer, so we need to take copies of the start and end locations of the register operand before calling it. Previously, the caret in the diagnostic pointer to the comma after the r0 operand in the test, rather than the start of the operand. Differential revision: https://reviews.llvm.org/D31537 llvm-svn: 314799
* [ARM, Asm] Fix ubsan failure caused by out-of-range enum valueOliver Stannard2017-10-031-2/+2
| | | | | | | | In this code, we use ~0U as a sentinel value for any operand class that doesn't have a user-friendly error message, but this value isn't in range of the MatchClassKind enum, so we need to ensure it does not get passed to isSubclass. llvm-svn: 314793
* [ARM, Asm] Remove dead code causing MSan failure.Oliver Stannard2017-10-031-7/+0
| | | | | | | r314779 caused ErrorInfo to be red uninitialised, but also made this code dead, so it can just be removed. llvm-svn: 314791
* [ARM] Use new assembler diags for ARMOliver Stannard2017-10-032-133/+289
| | | | | | | | | | | | | | | This converts the ARM AsmParser to use the new assembly matcher error reporting mechanism, which allows errors to be reported for multiple instruction encodings when it is ambiguous which one the user intended to use. By itself this doesn't improve many error messages, because we don't have diagnostic text for most operand types, but as we add that then this will allow more of those diagnostic strings to be used when they are relevant. Differential revision: https://reviews.llvm.org/D31530 llvm-svn: 314779
* ISel type legalization: add debug messages. NFCI.Sjoerd Meijer2017-10-031-0/+1
| | | | | | | | | | This adds some more debug messages to the type legalizer and functions like PromoteNode, ExpandNode, ExpandLibCall in an attempt to make the debug messages a little bit more informative and useful. Differential Revision: https://reviews.llvm.org/D38450 llvm-svn: 314773
* [SystemZ] implement shouldCoalesce()Jonas Paulsson2017-09-292-2/+6
| | | | | | | | | | | | | | | | | | | Implement shouldCoalesce() to help regalloc avoid running out of GR128 registers. If a COPY involving a subreg of a GR128 is coalesced, the live range of the GR128 virtual register will be extended. If this happens where there are enough phys-reg clobbers present, regalloc will run out of registers (if there is not a single GR128 allocatable register available). This patch tries to allow coalescing only when it can prove that this will be safe by checking the (local) interval in question. Review: Ulrich Weigand, Quentin Colombet https://reviews.llvm.org/D37899 https://bugs.llvm.org/show_bug.cgi?id=34610 llvm-svn: 314516
* [ARM] v8.3-a complex number supportSam Parker2017-09-297-2/+298
| | | | | | | | | | | | | | | New instructions are added to AArch32 and AArch64 to aid floating-point multiplication and addition of complex numbers, where the complex numbers are packed in a vector register as a pair of elements. The Imaginary part of the number is placed in the more significant element, and the Real part of the number is placed in the less significant element. This patch adds assembler for the ARM target. Differential Revision: https://reviews.llvm.org/D36789 llvm-svn: 314511
* ARM: Fix cases where CSI Restored bit is not clearedMatthias Braun2017-09-283-9/+19
| | | | | | | | | | LR is an untypical callee saved register in that it is restored into a different register (PC) and thus does not live-out of the return block. This case requires the `Restored` flag in CalleeSavedInfo to be cleared. This fixes a number of cases where this wasn't handled correctly yet. llvm-svn: 314471
* [ARM] Restore the right frame pointer register in Int_eh_sjlj_longjmpMartin Storsjo2017-09-281-14/+58
| | | | | | | | | | | | | | | | | | | | | | In setupEntryBlockAndCallSites in CodeGen/SjLjEHPrepare.cpp, we fetch and store the actual frame pointer, but on return via the longjmp intrinsic, it always was restored into the r7 variable. On windows, the frame pointer should be restored into r11 instead of r7. On Darwin (where sjlj exception handling is used by default), the frame pointer is always r7, both in arm and thumb mode, and likewise, on windows, the frame pointer always is r11. On linux however, if sjlj exception handling is enabled (which it isn't by default), libcxxabi and the user code can be built in differing modes using different registers as frame pointer. Therefore, when restoring registers on a platform where we don't always use the same register depending on code mode, restore both r7 and r11. Differential Revision: https://reviews.llvm.org/D38253 llvm-svn: 314451
* [ARM] Fix SJLJ exception handling when manually chosen on a platform where ↵Martin Storsjo2017-09-281-1/+3
| | | | | | | | it isn't default Differential Revision: https://reviews.llvm.org/D38252 llvm-svn: 314450
* [ARM] isTruncateFree fixSam Parker2017-09-271-6/+6
| | | | | | | | | | I implemented isTruncateFree in rL313533, this patch fixes the logic to match my comment, as the previous logic was too general. Now the only truncates that are free are i64 -> i32. Differential Revision: https://reviews.llvm.org/D38234 llvm-svn: 314280
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