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* [C++11,ARM64] Range based for loops in load/store pair optimizer.Jim Grosbach2014-04-021-4/+1
| | | | | | No functional change intended. llvm-svn: 205444
* [C++11,ARM64] Range based for loops in target lowering.Jim Grosbach2014-04-021-3/+2
| | | | | | No functional change intended. llvm-svn: 205443
* [C++11,ARM64] Range based for loops in frame lowering.Jim Grosbach2014-04-021-5/+3
| | | | | | No functional change intended. llvm-svn: 205442
* [C++11,ARM64] Range based for loops in pseudo expansion.Jim Grosbach2014-04-021-3/+2
| | | | | | No functional change intended. llvm-svn: 205441
* [C++11,ARM64] Range based for loops for LOHJim Grosbach2014-04-021-34/+21
| | | | | | No functional change intended. llvm-svn: 205440
* [C++11,ARM64] Range based for loops TLS cleanup.Jim Grosbach2014-04-021-3/+2
| | | | | | No functional change intended. llvm-svn: 205439
* [C++11,ARM64] Range based for loops in branch relaxation.Jim Grosbach2014-04-021-6/+5
| | | | | | No functional change intended. llvm-svn: 205438
* [C++11,ARM64] Range based for loops in address type promotion.Jim Grosbach2014-04-021-34/+25
| | | | | | No functional change intended. llvm-svn: 205437
* [ARM64][CollectLOH] Remove the link to the radar from the comments.Quentin Colombet2014-04-021-3/+0
| | | | llvm-svn: 205435
* ARM64: use GOT for weak symbols & PIC.Tim Northover2014-04-021-6/+23
| | | | | | | | | | Weak symbols cannot use the small code model's usual ADRP sequences since the instruction simply may not be able to encode a value of 0. This redirects them to use the GOT, which hopefully linkers are able to cope with even in the static relocation model. llvm-svn: 205426
* ARM64: fix lowering of fp128 fptosi/fptouiTim Northover2014-04-021-1/+6
| | | | | | | We were creating libcall nodes that returned an MVT::f128, when these particular operations actually return an int of some stripe. llvm-svn: 205425
* ARM64: make sure first argument to INSERT_SUBVECTOR has right type.Tim Northover2014-04-021-1/+1
| | | | | | | | Again, coalescing and other optimisations swiftly made the MachineInstrs consistent again, but when compiled at -O0 a bad INSERT_SUBREGISTER was produced. llvm-svn: 205423
* ARM64: convert fp16 narrowing ISel to pseudo-instructionTim Northover2014-04-023-13/+14
| | | | | | | | The previous attempt was fine with optimisations, but was actually rather cavalier with its types. When compiled at -O0, it produced invalid COPY MachineInstrs. llvm-svn: 205422
* [ARM64][CollectLOH] Add some comments to explain how the LOHsQuentin Colombet2014-04-021-1/+52
| | | | | | | framework works (for the compiler part), since the design document is not available. llvm-svn: 205379
* Fixing an MSVC warning about widening the result of a 32-bit shift ↵Aaron Ballman2014-04-011-1/+1
| | | | | | implicitly. No functional change intended. llvm-svn: 205304
* ARM64: add intrinsic for pmull (p64 x p64 = p128) operations.Tim Northover2014-04-011-0/+7
| | | | llvm-svn: 205302
* Fixing warnings in the MSVC build. No functional changes intended.Aaron Ballman2014-04-015-42/+42
| | | | llvm-svn: 205301
* ARM64: add patterns for more lane-wise ld1/st1 operations.Tim Northover2014-04-012-59/+80
| | | | llvm-svn: 205294
* ARM64: fix bug in ld3r (1d) SelectionDAG.Tim Northover2014-04-011-1/+1
| | | | llvm-svn: 205293
* Register allocator: set CSRFirstUseCost to 5 for ARM64.Manman Ren2014-03-311-0/+7
| | | | | | | | | | | | A value of 5 means if we have a split or spill option that has a really low cost (1 << 14 is the entry frequency), we will choose to spill or split the really cold path before using a callee-saved register. This gives us the performance benefit on SPECInt2k and is also conservative. rdar://16162005 llvm-svn: 205248
* ARM64: add extra patterns for scalar shiftsTim Northover2014-03-311-6/+12
| | | | llvm-svn: 205209
* ARM64: add extra scalar neg pattern & tests.Tim Northover2014-03-311-1/+2
| | | | llvm-svn: 205208
* ARM64: add patterns for scalar sqdmlal & sqdmlsl.Tim Northover2014-03-311-0/+9
| | | | llvm-svn: 205207
* ARM64: add more patterns for commuted fmsub operations.Tim Northover2014-03-311-0/+8
| | | | llvm-svn: 205206
* ARM64: shuffle patterns around for fmin/fmax & add tests.Tim Northover2014-03-311-8/+8
| | | | llvm-svn: 205205
* ARM64: add more scalar patterns for usqadd & suqadd.Tim Northover2014-03-311-7/+11
| | | | llvm-svn: 205204
* ARM64: add more scalar patterns for reciprocal ops.Tim Northover2014-03-311-0/+15
| | | | llvm-svn: 205203
* ARM64: add i64 scalar pattern for @llvm.arm64.absTim Northover2014-03-312-7/+3
| | | | | | This will be used by the Clang front-end code for vabsd_s64. llvm-svn: 205202
* ARM64: fix a couple of signed/unsigned comparison warnings.Tim Northover2014-03-312-3/+2
| | | | llvm-svn: 205174
* Try to fix MSan bootstrap bot: make ARM64Disassembler::getInstruction() ↵Alexey Samsonov2014-03-311-2/+2
| | | | | | always initialize Size argument. llvm-svn: 205171
* ARM64CollectLOH.cpp: Tweak \param. [-Wdocumentation]NAKAMURA Takumi2014-03-311-1/+1
| | | | llvm-svn: 205162
* [ARM64] Fix materialization of an fp128 zero immediate. There currentlyChandler Carruth2014-03-311-2/+3
| | | | | | | | | is not a pattern to lower this with clever instructions that zero the register, so restrict the zero immediate legality special case to f64 and f32 (the only two sizes which fmov seems to directly support). Fixes backend errors when building code such as libxml. llvm-svn: 205161
* [ARM64] Fix a heap-use-after-free spotted by ASan.Chandler Carruth2014-03-301-1/+1
| | | | | | | | StringRef::lower() returns a std::string. Better yet, we can now stop thinking about what it returns and write 'auto'. It does the right thing. =] llvm-svn: 205135
* ARM64: uncopy/paste helper functionTim Northover2014-03-301-5/+4
| | | | | | | | | It was doing functional but highly suspect operations on bools due to the more limited shifting operands supported by memory instructions. Should fix some MSVC warnings. llvm-svn: 205134
* ARM64: remove unused variablesTim Northover2014-03-301-4/+0
| | | | llvm-svn: 205133
* ARM64: override all the things.Tim Northover2014-03-307-149/+148
| | | | | | | | Actually, mostly only those in the top-level directory that already had a "virtual" attached. But it's the thought that counts and it's been a long day. llvm-svn: 205131
* Fix a few -Wdocumentation warningsDmitri Gribenko2014-03-294-13/+13
| | | | llvm-svn: 205116
* Detemplatize LOHDirective.Benjamin Kramer2014-03-292-22/+25
| | | | | | | | | | | The ARM64 backend uses it only as a container to keep an MCLOHType and Arguments around so give it its own little copy. The other functionality isn't used and we had a crazy method specialization hack in place to keep it working. Unfortunately that was incompatible with MSVC. Also range-ify a couple of loops while at it. llvm-svn: 205114
* ARM64: Remove unused helper function, make others static.Benjamin Kramer2014-03-293-45/+6
| | | | llvm-svn: 205112
* ARM64: format register strings without creating a local Twine.Tim Northover2014-03-291-5/+5
| | | | | | It was causing horrible failures on some build-bots. llvm-svn: 205105
* ARM64: use 64-bit constant even on 32-bit machinesTim Northover2014-03-291-1/+1
| | | | | | Another existing bot failure so no tests. llvm-svn: 205093
* ARM64: change format specifier to work on 32-bit targetsTim Northover2014-03-291-1/+1
| | | | | | Existing tests were failing. llvm-svn: 205092
* [ARM64] Fix 'assert("...")' to be 'assert(0 && "...")'. Otherwise, it isChandler Carruth2014-03-293-3/+3
| | | | | | | | | | | no assert at all. ;] Some of these should probably be switched to llvm_unreachable, but I didn't want to perturb the behavior in this patch. Found by -Wstring-conversion, which I'll try to turn on in CMake builds at least as it is finding useful things. llvm-svn: 205091
* ARM64: initial backend importTim Northover2014-03-2984-0/+58636
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
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