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* [ARM64] Rename LR to the UAL-compliant 'X30'.Bradley Smith2014-04-092-2/+2
| | | | llvm-svn: 205885
* [ARM64] Rename FP to the UAL-compliant 'X29'.Bradley Smith2014-04-092-2/+2
| | | | llvm-svn: 205884
* [ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be ↵Bradley Smith2014-04-092-1/+15
| | | | | | zero but should be decoded/disassembled with any value. llvm-svn: 205883
* [ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0.Bradley Smith2014-04-092-8/+24
| | | | llvm-svn: 205882
* [ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have ↵Bradley Smith2014-04-091-1/+5
| | | | | | the top bit of their immediate clear. llvm-svn: 205881
* [ARM64] Scaled fixed-point FCVTZSs should also have bit 29 set to zero.Bradley Smith2014-04-091-1/+1
| | | | llvm-svn: 205880
* [ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1.Bradley Smith2014-04-091-0/+6
| | | | llvm-svn: 205879
* [ARM64] Floating point to fixed point scaled conversions are only available ↵Bradley Smith2014-04-092-14/+22
| | | | | | on fcvtzs and fcvtzu. llvm-svn: 205878
* [ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64.Bradley Smith2014-04-092-1/+18
| | | | llvm-svn: 205877
* [ARM64] Add missing tlbi operands and error for extra/missing register on ↵Bradley Smith2014-04-092-0/+32
| | | | | | tlbi aliases. llvm-svn: 205876
* [ARM64] Rework system register parsing to overcome SPSel clash in MSR variants.Bradley Smith2014-04-092-141/+74
| | | | llvm-svn: 205875
* [ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and ↵Bradley Smith2014-04-092-4/+32
| | | | | | stores, so the unused register fields are set to all-ones canonically but are recognised with any value. llvm-svn: 205874
* [ARM64] Use PStateMapper to ensure that MSRcpsr operands are validated ↵Bradley Smith2014-04-091-2/+7
| | | | | | during disassembly. llvm-svn: 205873
* [ARM64] Remove PrefetchOp and use ARM64PRFM instead.Bradley Smith2014-04-093-81/+14
| | | | llvm-svn: 205872
* [ARM64] Add WZR to isGPR32Register, since every use needs to check for this ↵Bradley Smith2014-04-091-4/+3
| | | | | | anyway. llvm-svn: 205871
* [ARM64] Remove ARM64SYS.Bradley Smith2014-04-091-665/+0
| | | | llvm-svn: 205870
* [ARM64] Move CPSRField and DBarrier operands over to AArch64-style ↵Bradley Smith2014-04-092-50/+45
| | | | | | disassembly and assembly. This removes the last users of namespace ARM64SYS. llvm-svn: 205869
* [ARM64] Switch the decoder, disassembler, instprinter and asmparser over to ↵Bradley Smith2014-04-097-347/+107
| | | | | | using AArch64-style system registers, and fix up test failures discovered in the process. llvm-svn: 205868
* [ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64. ↵Bradley Smith2014-04-0917-13/+56
| | | | | | These files are required in the decoder, disassembler and parser, and a layering violation was imminent. llvm-svn: 205867
* [ARM64] Copy the named immediate operand mapping logic and enums from ↵Bradley Smith2014-04-093-0/+1822
| | | | | | AArch64. AArch64's named immediate mapping and parsing is much more advanced than ARM64's. No functionality change - they're currently living side by side while I switch uses over. llvm-svn: 205866
* [ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and ↵Bradley Smith2014-04-091-9/+20
| | | | | | also (for add/sub only) if shift=11. llvm-svn: 205865
* [ARM64] Add support for NV condition code (exists only for valid ↵Bradley Smith2014-04-092-27/+11
| | | | | | assembly/disassembly, equivilant to AL) llvm-svn: 205864
* [ARM64] Add missing 1Q -> 1q vector kind aliasBradley Smith2014-04-091-0/+2
| | | | llvm-svn: 205863
* [ARM64] Add parsing for vector lists such as {v0.8b-v3.8b}Bradley Smith2014-04-091-19/+43
| | | | llvm-svn: 205862
* [ARM64] Correctly alias LSL to UXTW for 32bit instruction variants, rather ↵Bradley Smith2014-04-091-3/+3
| | | | | | than UXTX llvm-svn: 205861
* [ARM64] STRHro and STRBro were not being decoded at all.Bradley Smith2014-04-091-0/+2
| | | | llvm-svn: 205860
* [ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB ↵Bradley Smith2014-04-091-0/+6
| | | | | | instructions is unallocated if shift > 4. llvm-svn: 205859
* [ARM64] Register-offset loads and stores with the 'option' field equal to ↵Bradley Smith2014-04-091-14/+5
| | | | | | 00x or 10x are undefined. llvm-svn: 205858
* ARM64: scalarize v1i64 mul operationTim Northover2014-04-091-0/+2
| | | | | | This is the second part of fixing PR19367. llvm-svn: 205836
* ARM64: add pattern for <1 x i64> custom not node.Tim Northover2014-04-091-0/+1
| | | | | | This should fix PR19367. llvm-svn: 205835
* [Constant Hoisting][ARM64] Enable constant hoisting for ARM64.Juergen Ributzka2014-04-081-13/+131
| | | | | | | | This implements the target-hooks for ARM64 to enable constant hoisting. This fixes <rdar://problem/14774662> and <rdar://problem/16381500>. llvm-svn: 205791
* ARM64: fix fmsub patterns which assumed accum operand was firstTim Northover2014-04-081-4/+7
| | | | | | | | | | Confusingly, the NEON fmla instructions put the accumulator first but the scalar versions put it at the end (like the fma lib function & LLVM's intrinsic). This should fix PR19345, assuming there's only one issue. llvm-svn: 205758
* Tidy up comments a bit.Jim Grosbach2014-04-071-41/+41
| | | | | | Punctuation, grammar, formatting, etc.. llvm-svn: 205749
* ARM64: Range based for loop in ARM64PromoteConstant passJim Grosbach2014-04-071-9/+7
| | | | llvm-svn: 205748
* ARM64: Clean up file header comment a bit.Jim Grosbach2014-04-071-11/+9
| | | | llvm-svn: 205747
* MachineInstr: introduce explicit_operands and implicit_operands rangesDavid Blaikie2014-04-051-4/+1
| | | | | | | Makes iteration over implicit and explicit machine operands more explicit (har har). Insipired by code review discussion for r205565. llvm-svn: 205680
* ARM64: handle v1i1 types arising from setcc properly.Tim Northover2014-04-041-0/+34
| | | | | | | | | | | | | | | | | | | | There were several overlapping problems here, and this solution is closely inspired by the one adopted in AArch64 in r201381. Firstly, scalarisation of v1i1 setcc operations simply fails if the input types are legal. This is fixed in LegalizeVectorTypes.cpp this time, and allows AArch64 code to be simplified slightly. Second, vselect with such a setcc feeding into it ends up in ScalarizeVectorOperand, where it's not handled. I experimented with an implementation, but found that whatever DAG came out was rather horrific. I think Hao's DAG combine approach is a good one for quality, though there are edge cases it won't catch (to be fixed separately). Should fix PR19335. llvm-svn: 205625
* ARM64: use regalloc-friendly COPY_TO_REGCLASS for bitcastsTim Northover2014-04-042-79/+39
| | | | | | | | | | | | | | | | | | The previous patterns directly inserted FMOV or INS instructions into the DAG for scalar_to_vector & bitconvert patterns. This is horribly inefficient and can generated lots more GPR <-> FPR register traffic than necessary. It's much better to emit instructions the register allocator understands so it can coalesce the copies when appropriate. It led to at least one ISelLowering hack to avoid the problems, which was incorrect for v1i64 (FPR64 has no dsub). It can now be removed entirely. This should also fix PR19331. llvm-svn: 205616
* ARM64: add 128-bit MLA operations to the custom selection code.Tim Northover2014-04-041-3/+9
| | | | | | | | | | | Without this change, the llvm_unreachable kicked in. The code pattern being spotted is rather non-canonical for 128-bit MLAs, but it can happen and there's no point in generating sub-optimal code for it just because it looks odd. Should fix PR19332. llvm-svn: 205615
* Make consistent use of MCPhysReg instead of uint16_t throughout the tree.Craig Topper2014-04-046-25/+25
| | | | llvm-svn: 205610
* Tidy up. Space before ':' in range-based for loops.Jim Grosbach2014-04-035-9/+9
| | | | llvm-svn: 205585
* Fix typo.Jim Grosbach2014-04-031-1/+1
| | | | llvm-svn: 205582
* [ARM64] Teach the ARM64DeadRegisterDefinition pass to respect implicit-defs.Lang Hames2014-04-031-0/+21
| | | | | | | | | | | | | When rematerializing through truncates, the coalescer may produce instructions with dead defs, but live implicit-defs of subregs: E.g. %X1<def,dead> = MOVi64imm 2, %W1<imp-def>; %X1:GPR64, %W1:GPR32 These instructions are live, and their definitions should not be rewritten. Fixes <rdar://problem/16492408> llvm-svn: 205565
* ARM64: always use i64 for the RHS of shift operationsTim Northover2014-04-033-81/+67
| | | | | | | | | | Switching between i32 and i64 based on the LHS type is a good idea in theory, but pre-legalisation uses i64 regardless of our choice, leading to potential ISel errors. Should fix PR19294. llvm-svn: 205519
* ARM64: don't generate __sincos_stret calls unless on MachOTim Northover2014-04-031-5/+10
| | | | | | This should fix PR19314. llvm-svn: 205514
* Make a few more range-based loops use explicit types.Jim Grosbach2014-04-022-2/+2
| | | | | | No functional change. llvm-svn: 205458
* Simplify resolveFrameIndex() signature.Jim Grosbach2014-04-022-4/+2
| | | | | | | | Just pass a MachineInstr reference rather than an MBB iterator. Creating a MachineInstr& is the first thing every implementation did anyway. llvm-svn: 205453
* Make some range based loop types more explicit.Jim Grosbach2014-04-022-6/+6
| | | | | | No functional change, but more readable code. llvm-svn: 205451
* [C++11,ARM64] Range based for and explicit 'override' in STP cleanup.Jim Grosbach2014-04-021-15/+13
| | | | | | No functional change intended. llvm-svn: 205446
* [C++11,ARM64] Range based for loops in constant promotion.Jim Grosbach2014-04-021-9/+6
| | | | | | No functional change intended. llvm-svn: 205445
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