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* AArch64/ARM64: add half as a storage type on ARM64.Tim Northover2014-04-154-15/+19
| | | | | | | This brings it into line with the AArch64 behaviour and should open the way for certain OpenCL features. llvm-svn: 206286
* AArch64/ARM64: copy patterns for fixed-point conversionsTim Northover2014-04-152-15/+98
| | | | | | | | Code is mostly copied directly across, with a slight extension of the ISelDAGToDAG function so that it can cope with the floating-point constants being behind a litpool. llvm-svn: 206285
* ARM64: add constraints to various FastISel operationsTim Northover2014-04-151-6/+13
| | | | llvm-svn: 206284
* AArch64/ARM64: add dp tests from AArch64Tim Northover2014-04-151-0/+5
| | | | llvm-svn: 206281
* ARM64AsmParser.cpp: Fix vg_leak in MC/ARM64/fp-encoding.s.NAKAMURA Takumi2014-04-151-0/+2
| | | | llvm-svn: 206279
* Optional hash symbol feature support for ARM64Stepan Dyatkovskiy2014-04-151-16/+37
| | | | | | http://reviews.llvm.org/D3328 llvm-svn: 206276
* [MC] Require an MCContext when constructing an MCDisassembler.Lang Hames2014-04-152-3/+5
| | | | | | | | | | | | | | | | This patch re-introduces the MCContext member that was removed from MCDisassembler in r206063, and requires that an MCContext be passed in at MCDisassembler construction time. (Previously the MCContext member had been initialized in an ad-hoc fashion after construction). The MCCContext member can be used by MCDisassembler sub-classes to construct constant or target-specific MCExprs. This patch updates disassemblers for in-tree targets, and provides the MCRegisterInfo instance that some disassemblers were using through the MCContext (previously those backends were constructing their own MCRegisterInfo instances). llvm-svn: 206241
* [ARM64,C++11]: Range'ify the dead-register-definition pass.Jim Grosbach2014-04-151-27/+23
| | | | | | Range-based for loops. No functional change intended. llvm-svn: 206239
* [ARM64][MC] Set the default CPU string to generic.Quentin Colombet2014-04-151-3/+1
| | | | llvm-svn: 206228
* [ARM64][MC] Set the default CPU to cyclone when initilizating the MC layer.Quentin Colombet2014-04-141-0/+6
| | | | | | | | This matches that ARM64Subtarget does for now. This is related to <rdar://problem/16573920> llvm-svn: 206211
* Fix for codegen bug that could cause illegal cmn instruction generationLouis Gerbarg2014-04-141-1/+16
| | | | | | | | | | | In rare cases the dead definition elimination pass code can cause illegal cmn instructions when it replaces dead registers on instructions that use unmaterialized frame indexes. This patch disables the dead definition optimization for instructions which include frame index operands. rdar://16438284 llvm-svn: 206208
* Add a flag to disable the ARM64DeadRegisterDefinitionsPassLouis Gerbarg2014-04-141-1/+10
| | | | | | | This patch adds a -arm64-dead-def-elimination flag so that it is possible to disable dead definition elimination. Includes test case. llvm-svn: 206207
* [ARM64] Port over missing subtarget features, and CPU definitions from AArch64.James Molloy2014-04-143-5/+52
| | | | llvm-svn: 206198
* ARM64: remove buggy REV16 pattern.Tim Northover2014-04-141-2/+1
| | | | | | The 32-bit pattern is still valid: 0123 -> 3210 -> 1032. llvm-svn: 206172
* AArch64/ARM64: enable directcond.ll test on ARM64.Tim Northover2014-04-141-0/+2
| | | | | | | Code change is because optimizeCompareInstr didn't know how to pull the condition code out of FCSEL instructions. llvm-svn: 206171
* ARM64: add patterns for csXYZ with reversed operands.Tim Northover2014-04-141-0/+13
| | | | | | | AArch64 tests for this, and it's obviously a good idea. Have to invert the condition code, of course. llvm-svn: 206170
* ARM64: add support for AArch64's addsub_ext.llTim Northover2014-04-141-1/+1
| | | | | | | | | There was one definite issue in ARM64 (the off-by-1 check for whether a shift could be folded in) and one difference that is probably correct: ARM64 didn't fold nodes with multiple uses into the arithmetic operations unless optimising for code size. llvm-svn: 206168
* ARM64: optimise (cmp x, (sub 0, y)) to (cmn x, y).Tim Northover2014-04-141-11/+30
| | | | | | | This transformation is only valid when being used for an EQ or NE comparison since the flags change otherwise. llvm-svn: 206167
* Make helper static and place random global into the llvm namespace.Benjamin Kramer2014-04-121-6/+5
| | | | llvm-svn: 206116
* [ARM64] Never hoist the shift value of a shift instruction.Juergen Ributzka2014-04-121-3/+7
| | | | | | | There is no need to check if we want to hoist the immediate value of an shift instruction. Simply return TCC_Free right away. llvm-svn: 206101
* [ARM64] Fix the cost model for cheap large constants.Juergen Ributzka2014-04-121-5/+9
| | | | | | | | | | | | | | Originally the cost model would give up for large constants and just return the maximum cost. This is not what we want for constant hoisting, because some of these constants are large in bitwidth, but are still cheap to materialize. This commit fixes the cost model to either return TCC_Free if the cost cannot be determined, or accurately calculate the cost even for large constants (bitwidth > 128). This fixes <rdar://problem/16591573>. llvm-svn: 206100
* Add ARM64 CLS patternsLouis Gerbarg2014-04-111-0/+6
| | | | | | | | | This patch adds patterns to generate the cls instruction ARM64. Includes tests for 64 bit and 32 bit operands. rdar://15611957 llvm-svn: 206079
* Remove redundant symbolization support from MCDisassembler interface.Lang Hames2014-04-115-219/+284
| | | | | | | | | | | | | | | | | MCDisassembler has an MCSymbolizer member that is meant to take care of symbolizing during disassembly, but it also has several methods that enable the disassembler to do symbolization internally (i.e. without an attached symbolizer object). There is no need for this duplication, but ARM64 had been making use of it. This patch moves the ARM64 symbolization logic out of ARM64Disassembler and into an ARM64ExternalSymbolizer class, and removes the duplicated MCSymbolizer functionality from the MCDisassembler interface. Symbolization will now be done exclusively through MCSymbolizers. There should be no impact on disassembly for any platform, but this allows us to tidy up the MCDisassembler interface and simplify the process of (and invariants related to) disassembler setup. llvm-svn: 206063
* Implement depth_first and inverse_depth_first range factory functions.David Blaikie2014-04-111-1/+1
| | | | | | | | | | | | | | Also updated as many loops as I could find using df_begin/idf_begin - strangely I found no uses of idf_begin. Is that just used out of tree? Also a few places couldn't use df_begin because either they used the member functions of the depth first iterators or had specific ordering constraints (I added a comment in the latter case). Based on a patch by Jim Grosbach. (Jim - you just had iterator_range<T> where you needed iterator_range<idf_iterator<T>>) llvm-svn: 206016
* [ARM64,C++11] Range'ify use-lists iterators in address type promotion.Jim Grosbach2014-04-111-8/+4
| | | | llvm-svn: 206013
* [ARM64,C++11]: Range'ify use-list iterators in DAGToDAG.Jim Grosbach2014-04-111-6/+3
| | | | llvm-svn: 206007
* [ARM64,C++11]: More range-based loop simplification.Jim Grosbach2014-04-111-3/+2
| | | | llvm-svn: 206006
* [ARM64,C++11]: Range'ify loops in InstrInfo.Jim Grosbach2014-04-101-10/+5
| | | | llvm-svn: 205992
* [ARM64,C++11]: Range'ify loops in the conditional-compare pass.Jim Grosbach2014-04-101-27/+25
| | | | llvm-svn: 205988
* ARM64/*/LLVMBuild.txt: Prune redundant deps.NAKAMURA Takumi2014-04-103-3/+3
| | | | llvm-svn: 205963
* LLVMBuild.txt: Add missing dependencies.NAKAMURA Takumi2014-04-102-2/+2
| | | | llvm-svn: 205962
* LLVMBuild.txt: Reformat.NAKAMURA Takumi2014-04-104-4/+0
| | | | llvm-svn: 205961
* Fix abuse of StringRef on ARM64SysReg::MRSMapper::toString(Val, Valid).NAKAMURA Takumi2014-04-101-4/+4
| | | | | FIXME: Could we use SmallString here? llvm-svn: 205950
* ARM64: add an explicit cast to silence a silly warningSaleem Abdulrasool2014-04-101-2/+4
| | | | | | | | | | GCC 4.8 complains with: warning: enumeral and non-enumeral type in conditional expression Although this is silly and harmless in this case, add an explicit cast to silence the warning. llvm-svn: 205949
* [ARM64] Fix immediate cost calculation for types larger than i64.Juergen Ributzka2014-04-101-1/+1
| | | | | | | | | | The immediate cost calculation code was hitting an assertion in the included test case, because APInt was still internally 128-bits. Truncating it to 64-bits fixed the issue. Fixes <rdar://problem/16572521>. llvm-svn: 205947
* Simple fix for build failures resulting from r205867.Bob Wilson2014-04-091-1/+1
| | | | llvm-svn: 205918
* Fix some doc and comment typosAlp Toker2014-04-097-13/+13
| | | | llvm-svn: 205899
* [ARM64] Change SYS without a register to an alias to make disassembling more ↵Bradley Smith2014-04-093-22/+10
| | | | | | consistant. llvm-svn: 205898
* [ARM64] Correctly disassemble ISB operand as ISB not DBarrier.Bradley Smith2014-04-091-1/+6
| | | | llvm-svn: 205897
* [ARM64] Properly support both apple and standard syntax for FMOVBradley Smith2014-04-091-11/+10
| | | | llvm-svn: 205896
* [ARM64] Flag setting logical/add/sub immediate instructions don't use SP.Bradley Smith2014-04-091-4/+14
| | | | llvm-svn: 205895
* [ARM64] Conditional branches must always print their condition code, even AL.Bradley Smith2014-04-091-2/+1
| | | | llvm-svn: 205894
* [ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers.Bradley Smith2014-04-091-2/+2
| | | | llvm-svn: 205893
* [ARM64] When printing a pre-indexed address with #0, the ', #0' is not optional.Bradley Smith2014-04-094-13/+67
| | | | llvm-svn: 205892
* [ARM64] Add missing shifted register MVN alias to ORNBradley Smith2014-04-092-0/+13
| | | | llvm-svn: 205891
* [ARM64] SXTW/UXTW are only valid aliases for 32-bit operations.Bradley Smith2014-04-091-1/+3
| | | | llvm-svn: 205890
* [ARM64] Fix canonicalisation of MOVs. MOV is too complex to be modelled by a ↵Bradley Smith2014-04-093-19/+93
| | | | | | dumb alias. llvm-svn: 205889
* [ARM64] Fixup ADR/ADRP parsing such that they accept immediates and all ↵Bradley Smith2014-04-092-41/+68
| | | | | | labels types llvm-svn: 205888
* [ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions.Bradley Smith2014-04-091-2/+2
| | | | llvm-svn: 205887
* [ARM64] Tighten up the special casing in emitting arithmetic extends. UXTW ↵Bradley Smith2014-04-091-2/+4
| | | | | | should only be translated when the instruction uses WSP, not SP. Vice versa for UXTX and 64-bit instructions. llvm-svn: 205886
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