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* [ARM64] Enable feature predicates for NEON / FP / CRYPTO.Kevin Qin2014-04-238-188/+330
| | | | | | | | AArch64 has feature predicates for NEON, FP and CRYPTO instructions. This allows the compiler to generate code without using FP, NEON or CRYPTO instructions. llvm-svn: 206949
* Fix the assembler to print a better relocatable expression errorKevin Enderby2014-04-221-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | diagnostic that includes location information. Currently if one has this assembly: .quad (0x1234 + (4 * SOME_VALUE)) where SOME_VALUE is undefined ones gets the less than useful error message with no location information: % clang -c x.s clang -cc1as: fatal error: error in backend: expected relocatable expression With this fix one now gets a more useful error message with location information: % clang -c x.s x.s:5:8: error: expected relocatable expression .quad (0x1234 + (4 * SOME_VALUE)) ^ To do this I plumbed the SMLoc through the MCObjectStreamer EmitValue() and EmitValueImpl() interfaces so it could be used when creating the MCFixup. rdar://12391022 llvm-svn: 206906
* AArch64/ARM64: make use of ANDS and BICS instructions for comparisons.Tim Northover2014-04-224-17/+42
| | | | llvm-svn: 206888
* AArch64/ARM64: add patterns for scalar_to_vector/extract pairsTim Northover2014-04-221-0/+4
| | | | llvm-svn: 206876
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-2220-23/+40
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
* [cleanup] Lift using directives, DEBUG_TYPE definitions, and even someChandler Carruth2014-04-225-10/+10
| | | | | | | | | | | | system headers above the includes of generated '.inc' files that actually contain code. In a few targets this was already done pretty consistently, but it wasn't done *really* consistently anywhere. It is strictly cleaner IMO and necessary in a bunch of places where the DEBUG_TYPE is referenced from the generated code. Consistency with the necessary places trumps. Hopefully the build bots are OK with the movement of intrin.h... llvm-svn: 206838
* [Modules] Make Support/Debug.h modular. This requires it to not changeChandler Carruth2014-04-211-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | behavior based on other files defining DEBUG_TYPE, which means it cannot define DEBUG_TYPE at all. This is actually better IMO as it forces folks to define relevant DEBUG_TYPEs for their files. However, it requires all files that currently use DEBUG(...) to define a DEBUG_TYPE if they don't already. I've updated all such files in LLVM and will do the same for other upstream projects. This still leaves one important change in how LLVM uses the DEBUG_TYPE macro going forward: we need to only define the macro *after* header files have been #include-ed. Previously, this wasn't possible because Debug.h required the macro to be pre-defined. This commit removes that. By defining DEBUG_TYPE after the includes two things are fixed: - Header files that need to provide a DEBUG_TYPE for some inline code can do so by defining the macro before their inline code and undef-ing it afterward so the macro does not escape. - We no longer have rampant ODR violations due to including headers with different DEBUG_TYPE definitions. This may be mostly an academic violation today, but with modules these types of violations are easy to check for and potentially very relevant. Where necessary to suppor headers with DEBUG_TYPE, I have moved the definitions below the includes in this commit. I plan to move the rest of the DEBUG_TYPE macros in LLVM in subsequent commits; this one is big enough. The comments in Debug.h, which were hilariously out of date already, have been updated to reflect the recommended practice going forward. llvm-svn: 206822
* ARM64: Refactor away a few redundant helpers.Jim Grosbach2014-04-211-66/+33
| | | | | | | | | The comment claimed that the register class information wasn't available in the assembly parser, but that's not really true. It's just annoying to get to. Replace the helper functions with references to the auto-generated information. llvm-svn: 206802
* ARM64: Improve diagnostics for malformed reg+reg addressing mode.Jim Grosbach2014-04-211-1/+12
| | | | | | | Make sure only general purpose registers are valid for offset regs and that 32-bit regs are only valid for sxtw and uxtw extends. llvm-svn: 206799
* Move helper functions earlier in the file.Jim Grosbach2014-04-211-54/+53
| | | | | | No functional change. llvm-svn: 206798
* ARM64: Extended addressing mode source reg is 64-bit.Jim Grosbach2014-04-211-5/+1
| | | | | | | | | | | | | | The canonical form for the extended addressing mode (e.g., "[x1, w2, uxtw #3]" is for the MCInst to have the second register be the full 64-bit GPR64 register class. The instruction printer cleans up the output for display to show the 32-bit register instead, per the specification. This simplifies 205893 now that the aliasing is handled in the printer in 206495 so that the codegen path and the disassembler path give the same MCInst form. llvm-svn: 206797
* ARM64: Combine shifts and uses from different basic block to bit-extract ↵Yi Jiang2014-04-212-3/+39
| | | | | | instruction llvm-svn: 206774
* Reapply r206732. This time without optimization of branches.Michael Zolotukhin2014-04-211-0/+2
| | | | llvm-svn: 206749
* Revert r206732 which is causing llc to crash on most of the build bots.Chandler Carruth2014-04-211-2/+0
| | | | | | | | Original commit message: Implement builtins for safe division: safe.sdiv.iN, safe.udiv.iN, safe.srem.iN, safe.urem.iN (iN = i8, i61, i32, or i64). llvm-svn: 206735
* Implement builtins for safe division: safe.sdiv.iN, safe.udiv.iN, safe.srem.iN,Michael Zolotukhin2014-04-211-0/+2
| | | | | | safe.urem.iN (iN = i8, i16, i32, or i64). llvm-svn: 206732
* [ARM64] Ports the Cortex-A53 Machine Model description from AArch64.Chad Rosier2014-04-183-4/+135
| | | | | | | | | | | | | Summary: This port includes the rudimentary latencies that were provided for the Cortex-A53 Machine Model in the AArch64 backend. It also changes the SchedAlias for COPY in the Cyclone model to an explicit WriteRes mapping to avoid conflicts in other subtargets. Differential Revision: http://reviews.llvm.org/D3427 Patch by Dave Estes <cestes@codeaurora.org>! llvm-svn: 206652
* ARM64: disable generation of .loh directives outside MachO.Tim Northover2014-04-181-1/+2
| | | | | | Part of PR19455. llvm-svn: 206611
* ARM64: don't emit .subsections_via_symbols on ELF.Tim Northover2014-04-181-7/+9
| | | | | | Part of PR19455. llvm-svn: 206610
* ARM64: add extra NEG pattern.Tim Northover2014-04-181-0/+2
| | | | llvm-svn: 206609
* AArch64/ARM64: add non-scalar lowering for more FCVT operations.Tim Northover2014-04-182-2/+12
| | | | llvm-svn: 206591
* AArch64/ARM64: improve spotting of EXT instructions from VECTOR_SHUFFLE.Tim Northover2014-04-181-5/+7
| | | | | | | We couldn't cope if the first mask element was UNDEF before, which isn't ideal. llvm-svn: 206588
* AArch64/ARM64: spot a greater variety of concat_vector operations.Tim Northover2014-04-181-14/+72
| | | | | | | | | | Code mostly copied from AArch64, just tidied up a trifle and plumbed into the ARM64 way of doing things. This also enables the AArch64 tests which inspired the previous untested commits. llvm-svn: 206574
* ARM64: implement cunning optimisation from AArch64Tim Northover2014-04-181-0/+53
| | | | | | | | A vector extract followed by a dup can become a single instruction even if the types don't match. AArch64 handled this in ISelLowering, but a few reasonably simple patterns can take care of it in TableGen, so that's where I've put it. llvm-svn: 206573
* ARM64: spot a vector_shuffle that maps to INS and expand.Tim Northover2014-04-181-0/+64
| | | | | | | Tests will be coming very shortly when all the optimisations needed to support AArch64's neon-copy.ll file are committed. llvm-svn: 206572
* ARM64: nick some AArch64 patterns for extract/insert -> INS.Tim Northover2014-04-181-0/+37
| | | | | | | Tests will be committed shortly when all optimisations needed to support AArch64's neon-copy.ll file are supported. llvm-svn: 206571
* AArch64/ARM64: emit all vector FP comparisons as such.Tim Northover2014-04-181-5/+42
| | | | | | | | | | | | ARM64 was scalarizing some vector comparisons which don't quite map to AArch64's compare and mask instructions. AArch64's approach of sacrificing a little efficiency to emulate them with the limited set available was better, so I ported it across. More "inspired by" than copy/paste since the backend's internal expectations were a bit different, but the tests were invaluable. llvm-svn: 206570
* AArch64/ARM64: port BSL logic from AArch64 & enable test.Tim Northover2014-04-183-0/+75
| | | | | | | | | | | I enhanced it a little in the process. The decision shouldn't really be beased on whether a BUILD_VECTOR is a splat: any set of constants will do the job provided they're related in the correct way. Also, the BUILD_VECTOR could be any operand of the incoming AND nodes, so it's best to check for all 4 possibilities rather than assuming it'll be the RHS. llvm-svn: 206569
* AArch64/ARM64: copy byval implementation from AArch64.Tim Northover2014-04-182-16/+49
| | | | | | | | It's not actually used to handle C or C++ ABI rules on ARM64, but could well be emitted by other language front-ends, so it's as well to have a sensible implementation. llvm-svn: 206568
* [ARM64,C++11] Range'ify another loop.Jim Grosbach2014-04-171-9/+7
| | | | llvm-svn: 206539
* Improve ARM64 vector creationLouis Gerbarg2014-04-172-2/+5
| | | | | | | | | | | This patch improves the performance of vector creation in caseiswhere where several of the lanes in the vector are a constant floating point value. It also includes new patterns to fold together some of the instructions when the value is 0.0f. Test cases included. rdar://16349427 llvm-svn: 206496
* ARM64: [su]xtw use W regs as inputs, not X regs.Jim Grosbach2014-04-171-4/+8
| | | | | | | | | Update the SXT[BHW]/UXTW instruction aliases and the shifted reg addressing mode handling. PR19455 and rdar://16650642 llvm-svn: 206495
* ARM64: switch to IR-based atomic operations.Tim Northover2014-04-174-812/+91
| | | | | | | | Goodbye code! (Game: spot the bug fixed by the change). llvm-svn: 206490
* ARM64: add acquire/release versions of the existing atomic intrinsics.Tim Northover2014-04-174-4/+112
| | | | | | | These will be needed to support IR-level lowering of atomic operations. llvm-svn: 206489
* [ARM64] Fix "Cannot select" for vector ctpopAdam Nemet2014-04-171-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit of r205855: Author: Arnold Schwaighofer <aschwaighofer@apple.com> Date: Wed Apr 9 14:20:47 2014 +0000 SLPVectorizer: Only vectorize intrinsics whose operands are widened equally The vectorizer only knows how to vectorize intrinics by widening all operands by the same factor. Patch by Tyler Nowicki! exposed a backend bug causing a regression (Cannot select ctpop). The commit msg is a bit confusing because the patch actually changes the behavior for the loop-vectorizer as well. As things got refactored into a helper ctpop got snuck in to the trivially-vectorizable helper which is now used by both vectorizers. In other words, we started seeing vector-ctpops in the backend. This change makes ctpop LegalizeAction::Expand for the types not supported by the byte-only CNT instruction. We may be able to custom-lower these later to a single CNT but this is to fix the compiler crash first. Fixes <rdar://problem/16578951> llvm-svn: 206433
* Replacing a non-ASCII character in a comment with an ASCII character. Fixes ↵Aaron Ballman2014-04-161-1/+1
| | | | | | a C4819 warning in MSVC. llvm-svn: 206403
* ARM64: silence sign-comparison warning.Tim Northover2014-04-161-1/+1
| | | | llvm-svn: 206393
* AArch64/ARM64: produce correct relocation for conditional branches.Tim Northover2014-04-161-1/+5
| | | | llvm-svn: 206391
* AArch64/ARM64: port across stub handling for ELF C++ exceptions.Tim Northover2014-04-161-2/+33
| | | | | | | | The most important part here is that we should actuall emit the stubs we refer to in the exception table, but as a side issue this uses more sensible & GCC compatible representations for some of the bits of information. llvm-svn: 206380
* ARM64: use 32-bit moves for constants where possible.Tim Northover2014-04-162-8/+24
| | | | | | | | | | | | If we know that a particular 64-bit constant has all high bits zero, then we can rely on the fact that 32-bit ARM64 instructions automatically zero out the high bits of an x-register. This gives the expansion logic less constraints to satisfy and so sometimes allows it to pick better sequences. Came up while porting test/CodeGen/AArch64/movw-consts.ll: this will allow a 32-bit MOVN to be used in @test8 soon. llvm-svn: 206379
* ARM64: use the integrated assembler on ELF.Tim Northover2014-04-161-0/+2
| | | | llvm-svn: 206378
* Fixing a compile error in debug versions of MSVC. It seems that the ↵Aaron Ballman2014-04-161-1/+2
| | | | | | range-based for loop is confused by the DEBUG macro expansion unless a compound statement is used. llvm-svn: 206376
* ARM64: mark x7 as used when an i128 gets shunted onto the stack.Tim Northover2014-04-161-1/+1
| | | | | | | | The second half of a split i128 was ending up in x7, which is not a good thing. This is another part of PR19432. llvm-svn: 206366
* [ARM64,C++11] Tidy up branch relaxation a bit w/ c++11.Jim Grosbach2014-04-161-32/+25
| | | | | | No functional change. llvm-svn: 206344
* ARM64: Nuke some dead code.Jim Grosbach2014-04-161-1/+0
| | | | | | Missed in previous commit. llvm-svn: 206343
* [ARM64,C++11] Clean up the ARM64 LOH collection pass.Jim Grosbach2014-04-151-155/+114
| | | | | | | | Range'ify a bunch of loops, mainly. As a result, we have a variety of objects via reference rather than by pointer, so propogate that through the various helper functions where it makes sense. llvm-svn: 206337
* [ARM64] Set default CPU to generic instead of cyclone.Quentin Colombet2014-04-151-3/+1
| | | | llvm-svn: 206313
* AArch64/ARM64: add missing pattern for extending load.Tim Northover2014-04-151-0/+2
| | | | llvm-svn: 206290
* AArch64/ARM64: only mangle MOVZ/MOVN during encoding when neededTim Northover2014-04-151-0/+16
| | | | | | | | Sometimes we need emit the bits that would actually be a MOVN when producing a relocated MOVZ instruction (don't ask). But not always, a check which ARM64 got wrong until now. llvm-svn: 206289
* AArch64/ARM64: add support for large code-model jump tables.Tim Northover2014-04-152-0/+18
| | | | | | | I've left the MachO CodeGen as it is, there's a reasonable chance it should use the GOT like ConstPools, but I'm not certain. llvm-svn: 206288
* AArch64/ARM64: add patterns for various commutations of FNMADD.Tim Northover2014-04-151-0/+14
| | | | llvm-svn: 206287
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