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* [MC] Require an MCContext when constructing an MCDisassembler.Lang Hames2014-04-151-2/+3
| | | | | | | | | | | | | | | | This patch re-introduces the MCContext member that was removed from MCDisassembler in r206063, and requires that an MCContext be passed in at MCDisassembler construction time. (Previously the MCContext member had been initialized in an ad-hoc fashion after construction). The MCCContext member can be used by MCDisassembler sub-classes to construct constant or target-specific MCExprs. This patch updates disassemblers for in-tree targets, and provides the MCRegisterInfo instance that some disassemblers were using through the MCContext (previously those backends were constructing their own MCRegisterInfo instances). llvm-svn: 206241
* Make helper static and place random global into the llvm namespace.Benjamin Kramer2014-04-121-6/+5
| | | | llvm-svn: 206116
* Remove redundant symbolization support from MCDisassembler interface.Lang Hames2014-04-111-205/+20
| | | | | | | | | | | | | | | | | MCDisassembler has an MCSymbolizer member that is meant to take care of symbolizing during disassembly, but it also has several methods that enable the disassembler to do symbolization internally (i.e. without an attached symbolizer object). There is no need for this duplication, but ARM64 had been making use of it. This patch moves the ARM64 symbolization logic out of ARM64Disassembler and into an ARM64ExternalSymbolizer class, and removes the duplicated MCSymbolizer functionality from the MCDisassembler interface. Symbolization will now be done exclusively through MCSymbolizers. There should be no impact on disassembly for any platform, but this allows us to tidy up the MCDisassembler interface and simplify the process of (and invariants related to) disassembler setup. llvm-svn: 206063
* [ARM64] Flag setting logical/add/sub immediate instructions don't use SP.Bradley Smith2014-04-091-4/+14
| | | | llvm-svn: 205895
* [ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers.Bradley Smith2014-04-091-2/+2
| | | | llvm-svn: 205893
* [ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions.Bradley Smith2014-04-091-2/+2
| | | | llvm-svn: 205887
* [ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0.Bradley Smith2014-04-091-6/+18
| | | | llvm-svn: 205882
* [ARM64] Use PStateMapper to ensure that MSRcpsr operands are validated ↵Bradley Smith2014-04-091-2/+7
| | | | | | during disassembly. llvm-svn: 205873
* [ARM64] Switch the decoder, disassembler, instprinter and asmparser over to ↵Bradley Smith2014-04-091-7/+26
| | | | | | using AArch64-style system registers, and fix up test failures discovered in the process. llvm-svn: 205868
* [ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64. ↵Bradley Smith2014-04-091-1/+1
| | | | | | These files are required in the decoder, disassembler and parser, and a layering violation was imminent. llvm-svn: 205867
* [ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and ↵Bradley Smith2014-04-091-9/+20
| | | | | | also (for add/sub only) if shift=11. llvm-svn: 205865
* [ARM64] STRHro and STRBro were not being decoded at all.Bradley Smith2014-04-091-0/+2
| | | | llvm-svn: 205860
* [ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB ↵Bradley Smith2014-04-091-0/+6
| | | | | | instructions is unallocated if shift > 4. llvm-svn: 205859
* [ARM64] Register-offset loads and stores with the 'option' field equal to ↵Bradley Smith2014-04-091-14/+5
| | | | | | 00x or 10x are undefined. llvm-svn: 205858
* Fixing warnings in the MSVC build. No functional changes intended.Aaron Ballman2014-04-011-2/+2
| | | | llvm-svn: 205301
* Try to fix MSan bootstrap bot: make ARM64Disassembler::getInstruction() ↵Alexey Samsonov2014-03-311-2/+2
| | | | | | always initialize Size argument. llvm-svn: 205171
* [ARM64] Fix 'assert("...")' to be 'assert(0 && "...")'. Otherwise, it isChandler Carruth2014-03-291-1/+1
| | | | | | | | | | | no assert at all. ;] Some of these should probably be switched to llvm_unreachable, but I didn't want to perturb the behavior in this patch. Found by -Wstring-conversion, which I'll try to turn on in CMake builds at least as it is finding useful things. llvm-svn: 205091
* ARM64: initial backend importTim Northover2014-03-291-0/+2142
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
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