| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix use after free in Thumb2SizeReduction (PR4707). A MachineInstr was used ↵ | Benjamin Kramer | 2009-08-16 | 1 | -1/+4 |
| | | | | | | | after erasure. llvm-svn: 79189 | ||||
| * | Turn on if-conversion for thumb2. | Evan Cheng | 2009-08-15 | 1 | -6/+14 |
| | | | | | llvm-svn: 79084 | ||||
| * | Shrink ADR and LDR from constantpool late during constantpool island pass. | Evan Cheng | 2009-08-14 | 1 | -0/+2 |
| | | | | | llvm-svn: 78970 | ||||
| * | PredCC is meant to be 2 bits wide, like PredCC1. | Evan Cheng | 2009-08-12 | 1 | -1/+1 |
| | | | | | llvm-svn: 78829 | ||||
| * | Shrink Thumb2 movcc instructions. | Evan Cheng | 2009-08-12 | 1 | -1/+2 |
| | | | | | llvm-svn: 78790 | ||||
| * | Shrink ADDS, ADC, RSB, and SUBS. | Evan Cheng | 2009-08-12 | 1 | -29/+103 |
| | | | | | llvm-svn: 78776 | ||||
| * | Shrinkify Thumb2 r = add sp, imm. | Evan Cheng | 2009-08-11 | 1 | -7/+18 |
| | | | | | llvm-svn: 78745 | ||||
| * | Shrinkify Thumb2 load / store multiple instructions. | Evan Cheng | 2009-08-11 | 1 | -34/+84 |
| | | | | | llvm-svn: 78717 | ||||
| * | Fix the previous accidental commit. Now shrinking common Thumb2 load / store ↵ | Evan Cheng | 2009-08-11 | 1 | -2/+4 |
| | | | | | | | instructions. llvm-svn: 78659 | ||||
| * | Fix Thumb2 load / store addressing mode matching code. Do not use so_reg form to | Evan Cheng | 2009-08-11 | 1 | -2/+140 |
| | | | | | | | | | | | match base only address, i.e. [r] since Thumb2 requires a offset register field. For those, use [r + imm12] where the immediate is zero. Note the generated assembly code does not look any different after the patch. But the bug would have broken the JIT (if there is Thumb2 support) and it can break later passes which expect the address mode to be well-formed. llvm-svn: 78658 | ||||
| * | Watch out for empty BB. | Evan Cheng | 2009-08-10 | 1 | -1/+1 |
| | | | | | llvm-svn: 78562 | ||||
| * | rev, rev16, and revsh do not set CPSR. | Evan Cheng | 2009-08-10 | 1 | -3/+3 |
| | | | | | llvm-svn: 78561 | ||||
| * | Duh. Most 16-bit Thumb rr instructions are two-address. Fix table. | Evan Cheng | 2009-08-10 | 1 | -9/+15 |
| | | | | | llvm-svn: 78560 | ||||
| * | CPSR can be livein; transfer predicate operands correctly; tMUL is two-address. | Evan Cheng | 2009-08-10 | 1 | -19/+57 |
| | | | | | llvm-svn: 78559 | ||||
| * | Add support to reduce most of 32-bit Thumb2 arithmetic instructions. | Evan Cheng | 2009-08-10 | 1 | -69/+147 |
| | | | | | llvm-svn: 78550 | ||||
| * | Add support to convert 32-bit instructions to 16-bit non-two-address ones. | Evan Cheng | 2009-08-09 | 1 | -35/+96 |
| | | | | | llvm-svn: 78540 | ||||
| * | Add a skeleton Thumb2 instruction size reduction pass. | Evan Cheng | 2009-08-08 | 1 | -0/+213 |
| llvm-svn: 78456 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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