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path: root/llvm/lib/Target/ARM/Thumb2RegisterInfo.cpp
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* Implement frame unwinding information emission for Thumb1. Not finished yet ↵Anton Korobeynikov2011-03-051-8/+10
| | | | | | because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed. llvm-svn: 127104
* Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov2011-01-101-1/+0
| | | | | | and fixes here and there. llvm-svn: 123170
* Add const qualifiers to CodeGen's use of LLVM IR constructs.Dan Gohman2010-04-151-1/+1
| | | | llvm-svn: 101334
* Cleanup now that frame index scavenging via post-pass is working for ARM and ↵Jim Grosbach2009-10-281-5/+0
| | | | | | Thumb2. llvm-svn: 85406
* 80-column cleanupJim Grosbach2009-10-251-2/+3
| | | | llvm-svn: 85064
* Trim more includes.Evan Cheng2009-10-221-1/+0
| | | | llvm-svn: 84832
* Push LLVMContexts through the IntegerType APIs.Owen Anderson2009-08-131-1/+2
| | | | llvm-svn: 78948
* - More refactoring. This gets rid of all of the getOpcode calls.Evan Cheng2009-07-281-211/+0
| | | | | | | | | | | - This change also makes it possible to switch between ARM / Thumb on a per-function basis. - Fixed thumb2 routine which expand reg + arbitrary immediate. It was using using ARM so_imm logic. - Use movw and movt to do reg + imm when profitable. - Other code clean ups and minor optimizations. llvm-svn: 77300
* Refactor. Get rid of a few more getOpcode() calls.Evan Cheng2009-07-261-4/+5
| | | | llvm-svn: 77164
* Get rid of a couple of unnecessary getOpcode calls.Evan Cheng2009-07-251-1/+1
| | | | llvm-svn: 77035
* Revert the ConstantInt constructors back to their 2.5 forms where possible, ↵Owen Anderson2009-07-241-2/+1
| | | | | | thanks to contexts-on-types. More to come. llvm-svn: 77011
* Thumb2 should use the register scavenger.Evan Cheng2009-07-241-2/+1
| | | | llvm-svn: 76930
* Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index ↵David Goodwin2009-07-241-0/+210
| | | | | | elimination more exactly for Thumb-2 to get better code gen. llvm-svn: 76919
* Get rid of the Pass+Context magic.Owen Anderson2009-07-221-1/+1
| | | | llvm-svn: 76702
* Let callers decide the sub-register index on the def operand of ↵Evan Cheng2009-07-161-2/+4
| | | | | | | | rematerialized instructions. Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right. llvm-svn: 75900
* Move EVER MORE stuff over to LLVMContext.Owen Anderson2009-07-141-1/+4
| | | | llvm-svn: 75703
* Use common code for both ARM and Thumb-2 instruction and register info.David Goodwin2009-07-081-697/+4
| | | | llvm-svn: 75067
* Implement changes from Chris's feedback.Torok Edwin2009-07-081-2/+1
| | | | | | Finish converting lib/Target. llvm-svn: 75043
* Generalize opcode selection in ARMBaseRegisterInfo.David Goodwin2009-07-081-6/+7
| | | | llvm-svn: 75036
* Push methods into base class in preparation for sharing.David Goodwin2009-07-081-6/+7
| | | | llvm-svn: 75020
* Start converting to new error handling API.Torok Edwin2009-07-081-2/+2
| | | | | | | cerr+abort -> llvm_report_error assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included) llvm-svn: 75018
* Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into ↵David Goodwin2009-07-021-0/+755
Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2. llvm-svn: 74731
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