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path: root/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
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* In Thumb1, the register scavenger is not always able to use an emergencyJim Grosbach2009-10-051-0/+25
| | | | | | | | spill slot. When frame references are via the frame pointer, they will be negative, but Thumb1 load/store instructions only allow positive immediate offsets. Instead, Thumb1 will spill to R12. llvm-svn: 83336
* ARM::tPOP and tPOP_RET each has an extra writeback operand now.Evan Cheng2009-10-011-0/+1
| | | | llvm-svn: 83214
* Start of revamping the register scavenging in PEI. ARM Thumb1 is the drivingJim Grosbach2009-09-241-53/+83
| | | | | | | | | | | | | | | | | | | interest for this, as it currently reserves a register rather than using the scavenger for matierializing constants as needed. Instead of scavenging registers on the fly while eliminating frame indices, new virtual registers are created, and then a scavenged collectively in a post-pass over the function. This isolates the bits that need to interact with the scavenger, and sets the stage for more intelligent use, and reuse, of scavenged registers. For the time being, this is disabled by default. Once the bugs are worked out, the current scavenging calls in replaceFrameIndices() will be removed and the post-pass scavenging will be the default. Until then, -enable-frame-index-scavenging enables the new code. Currently, only the Thumb1 back end is set up to use it. llvm-svn: 82734
* Remove some unused variables and methods warned about byDuncan Sands2009-09-061-2/+1
| | | | | | icc (#177, partial). Patch by Erick Tryzelaar. llvm-svn: 81106
* Push LLVMContexts through the IntegerType APIs.Owen Anderson2009-08-131-1/+2
| | | | llvm-svn: 78948
* Shrinkify Thumb2 load / store multiple instructions.Evan Cheng2009-08-111-1/+1
| | | | llvm-svn: 78717
* Whitespace cleanup. Remove trailing whitespace.Jim Grosbach2009-08-111-1/+1
| | | | llvm-svn: 78666
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson2009-08-101-1/+1
| | | | | | own struct type. llvm-svn: 78610
* tADDrSPI doesn't have a predicate operand, but tADDhirr and tADDi3 have.Evan Cheng2009-07-281-0/+5
| | | | llvm-svn: 77305
* - More refactoring. This gets rid of all of the getOpcode calls.Evan Cheng2009-07-281-2/+2
| | | | | | | | | | | - This change also makes it possible to switch between ARM / Thumb on a per-function basis. - Fixed thumb2 routine which expand reg + arbitrary immediate. It was using using ARM so_imm logic. - Use movw and movt to do reg + imm when profitable. - Other code clean ups and minor optimizations. llvm-svn: 77300
* Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a ↵Evan Cheng2009-07-261-8/+8
| | | | | | low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir. llvm-svn: 77172
* Refactor. Get rid of a few more getOpcode() calls.Evan Cheng2009-07-261-0/+1
| | | | llvm-svn: 77164
* Revert the ConstantInt constructors back to their 2.5 forms where possible, ↵Owen Anderson2009-07-241-2/+1
| | | | | | thanks to contexts-on-types. More to come. llvm-svn: 77011
* Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index ↵David Goodwin2009-07-241-0/+9
| | | | | | elimination more exactly for Thumb-2 to get better code gen. llvm-svn: 76919
* Get rid of the Pass+Context magic.Owen Anderson2009-07-221-1/+1
| | | | llvm-svn: 76702
* Fix PR4567. Thumb1 target was using the wrong instruction to handle sp = sub ↵Evan Cheng2009-07-201-3/+11
| | | | | | fp, #c. llvm-svn: 76401
* Fix a regression from 76124. Thumb1 instructions default to S bit being true.Evan Cheng2009-07-191-13/+14
| | | | llvm-svn: 76374
* Emit cross regclass register moves for thumb2.Anton Korobeynikov2009-07-161-10/+0
| | | | | | Minor code duplication cleanup. llvm-svn: 76124
* Let callers decide the sub-register index on the def operand of ↵Evan Cheng2009-07-161-6/+8
| | | | | | | | rematerialized instructions. Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right. llvm-svn: 75900
* Move EVER MORE stuff over to LLVMContext.Owen Anderson2009-07-141-1/+4
| | | | llvm-svn: 75703
* llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin2009-07-141-1/+1
| | | | | | | | | This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
* Major changes to Thumb (not Thumb2). Many 16-bit instructions either ↵Evan Cheng2009-07-111-28/+96
| | | | | | | | modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically. A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well. llvm-svn: 75359
* Implement changes from Chris's feedback.Torok Edwin2009-07-081-0/+1
| | | | | | Finish converting lib/Target. llvm-svn: 75043
* Generalize opcode selection in ARMBaseRegisterInfo.David Goodwin2009-07-081-5/+6
| | | | llvm-svn: 75036
* Push methods into base class in preparation for sharing.David Goodwin2009-07-081-6/+7
| | | | llvm-svn: 75020
* Start converting to new error handling API.Torok Edwin2009-07-081-2/+2
| | | | | | | cerr+abort -> llvm_report_error assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included) llvm-svn: 75018
* Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into ↵David Goodwin2009-07-021-0/+755
Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2. llvm-svn: 74731
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